?? and2.vhd
字號:
library IEEE;
use IEEE.std_logic_1164.all;
entity and2 is
port (
c: out STD_LOGIC;
a: in STD_LOGIC;
b: in STD_LOGIC
);
end and2;
architecture and2_arch of and2 is
begin
c <= a and b ;-- <<enter your statements here>>
end and2_arch;
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