?? addr.vhd
字號:
library IEEE;
use IEEE.std_logic_1164.all;
entity addr is
port (
a: in STD_LOGIC;
b: in STD_LOGIC;
ci: in STD_LOGIC;
sum: out STD_LOGIC;
co: out STD_LOGIC
);
end addr;
architecture addr_arch of addr is
begin
sum<= a xor b xor ci ;
co <= (( a or b) and ci) or ( a and b);
-- <<enter your statements here>>
end addr_arch;
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