?? digital6counter.tan.rpt
字號(hào):
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock' ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------+-----------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------+-----------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 17.67 MHz ( period = 56.600 ns ) ; counter:inst6|counter[1] ; choice1from6:inst8|led_bits[1] ; clock ; clock ; None ; None ; 6.700 ns ;
; N/A ; 17.67 MHz ( period = 56.600 ns ) ; counter:inst6|counter[0] ; choice1from6:inst8|led_bits[0] ; clock ; clock ; None ; None ; 6.700 ns ;
; N/A ; 17.70 MHz ( period = 56.500 ns ) ; counter:inst6|counter[3] ; choice1from6:inst8|led_bits[3] ; clock ; clock ; None ; None ; 6.600 ns ;
; N/A ; 17.70 MHz ( period = 56.500 ns ) ; counter:inst6|counter[2] ; choice1from6:inst8|led_bits[2] ; clock ; clock ; None ; None ; 6.600 ns ;
; N/A ; 19.92 MHz ( period = 50.200 ns ) ; counter:inst7|counter[3] ; choice1from6:inst8|led_bits[3] ; clock ; clock ; None ; None ; 6.700 ns ;
; N/A ; 19.92 MHz ( period = 50.200 ns ) ; counter:inst7|counter[2] ; choice1from6:inst8|led_bits[2] ; clock ; clock ; None ; None ; 6.700 ns ;
; N/A ; 19.92 MHz ( period = 50.200 ns ) ; counter:inst7|counter[1] ; choice1from6:inst8|led_bits[1] ; clock ; clock ; None ; None ; 6.700 ns ;
; N/A ; 19.92 MHz ( period = 50.200 ns ) ; counter:inst7|counter[0] ; choice1from6:inst8|led_bits[0] ; clock ; clock ; None ; None ; 6.700 ns ;
; N/A ; 23.36 MHz ( period = 42.800 ns ) ; counter:inst5|counter[3] ; choice1from6:inst8|led_bits[3] ; clock ; clock ; None ; None ; 5.800 ns ;
; N/A ; 23.36 MHz ( period = 42.800 ns ) ; counter:inst5|counter[2] ; choice1from6:inst8|led_bits[2] ; clock ; clock ; None ; None ; 5.800 ns ;
; N/A ; 23.36 MHz ( period = 42.800 ns ) ; counter:inst5|counter[1] ; choice1from6:inst8|led_bits[1] ; clock ; clock ; None ; None ; 5.800 ns ;
; N/A ; 23.36 MHz ( period = 42.800 ns ) ; counter:inst5|counter[0] ; choice1from6:inst8|led_bits[0] ; clock ; clock ; None ; None ; 5.800 ns ;
; N/A ; 27.55 MHz ( period = 36.300 ns ) ; counter:inst4|counter[3] ; choice1from6:inst8|led_bits[3] ; clock ; clock ; None ; None ; 5.800 ns ;
; N/A ; 27.55 MHz ( period = 36.300 ns ) ; counter:inst4|counter[2] ; choice1from6:inst8|led_bits[2] ; clock ; clock ; None ; None ; 5.800 ns ;
; N/A ; 27.55 MHz ( period = 36.300 ns ) ; counter:inst4|counter[1] ; choice1from6:inst8|led_bits[1] ; clock ; clock ; None ; None ; 5.800 ns ;
; N/A ; 27.55 MHz ( period = 36.300 ns ) ; counter:inst4|counter[0] ; choice1from6:inst8|led_bits[0] ; clock ; clock ; None ; None ; 5.800 ns ;
; N/A ; 33.56 MHz ( period = 29.800 ns ) ; counter:inst3|counter[3] ; choice1from6:inst8|led_bits[3] ; clock ; clock ; None ; None ; 5.800 ns ;
; N/A ; 33.56 MHz ( period = 29.800 ns ) ; counter:inst3|counter[2] ; choice1from6:inst8|led_bits[2] ; clock ; clock ; None ; None ; 5.800 ns ;
; N/A ; 33.67 MHz ( period = 29.700 ns ) ; counter:inst3|counter[1] ; choice1from6:inst8|led_bits[1] ; clock ; clock ; None ; None ; 5.700 ns ;
; N/A ; 33.67 MHz ( period = 29.700 ns ) ; counter:inst3|counter[0] ; choice1from6:inst8|led_bits[0] ; clock ; clock ; None ; None ; 5.700 ns ;
; N/A ; 42.92 MHz ( period = 23.300 ns ) ; counter:inst2|counter[1] ; choice1from6:inst8|led_bits[1] ; clock ; clock ; None ; None ; 5.800 ns ;
; N/A ; 42.92 MHz ( period = 23.300 ns ) ; counter:inst2|counter[0] ; choice1from6:inst8|led_bits[0] ; clock ; clock ; None ; None ; 5.800 ns ;
; N/A ; 43.10 MHz ( period = 23.200 ns ) ; counter:inst2|counter[3] ; choice1from6:inst8|led_bits[3] ; clock ; clock ; None ; None ; 5.700 ns ;
; N/A ; 43.10 MHz ( period = 23.200 ns ) ; counter:inst2|counter[2] ; choice1from6:inst8|led_bits[2] ; clock ; clock ; None ; None ; 5.700 ns ;
; N/A ; 89.29 MHz ( period = 11.200 ns ) ; choice1from6:inst8|next_led_cs[1] ; choice1from6:inst8|led_bits[3] ; clock ; clock ; None ; None ; 6.700 ns ;
; N/A ; 89.29 MHz ( period = 11.200 ns ) ; choice1from6:inst8|next_led_cs[0] ; choice1from6:inst8|led_bits[3] ; clock ; clock ; None ; None ; 6.700 ns ;
; N/A ; 89.29 MHz ( period = 11.200 ns ) ; choice1from6:inst8|next_led_cs[5] ; choice1from6:inst8|led_bits[3] ; clock ; clock ; None ; None ; 6.700 ns ;
; N/A ; 89.29 MHz ( period = 11.200 ns ) ; choice1from6:inst8|next_led_cs[4] ; choice1from6:inst8|led_bits[3] ; clock ; clock ; None ; None ; 6.700 ns ;
; N/A ; 89.29 MHz ( period = 11.200 ns ) ; choice1from6:inst8|next_led_cs[3] ; choice1from6:inst8|led_bits[3] ; clock ; clock ; None ; None ; 6.700 ns ;
; N/A ; 89.29 MHz ( period = 11.200 ns ) ; choice1from6:inst8|next_led_cs[2] ; choice1from6:inst8|led_bits[3] ; clock ; clock ; None ; None ; 6.700 ns ;
; N/A ; 89.29 MHz ( period = 11.200 ns ) ; choice1from6:inst8|next_led_cs[1] ; choice1from6:inst8|led_bits[2] ; clock ; clock ; None ; None ; 6.700 ns ;
; N/A ; 89.29 MHz ( period = 11.200 ns ) ; choice1from6:inst8|next_led_cs[0] ; choice1from6:inst8|led_bits[2] ; clock ; clock ; None ; None ; 6.700 ns ;
; N/A ; 89.29 MHz ( period = 11.200 ns ) ; choice1from6:inst8|next_led_cs[5] ; choice1from6:inst8|led_bits[2] ; clock ; clock ; None ; None ; 6.700 ns ;
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