{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 24 23:23:32 2007 " "Info: Processing started: Sat Mar 24 23:23:32 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Digital6Counter -c Digital6Counter " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Digital6Counter -c Digital6Counter" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter-counter_architecture " "Info: Found design unit 1: counter-counter_architecture" {  } { { "counter.vhd" "" { Text "H:/03-源碼文件/VHDL/03-數(shù)字鐘/counter.vhd" 57 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "counter.vhd" "" { Text "H:/03-源碼文件/VHDL/03-數(shù)字鐘/counter.vhd" 38 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "leddrv.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file leddrv.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 leddrv-leddrv_architecture " "Info: Found design unit 1: leddrv-leddrv_architecture" {  } { { "leddrv.vhd" "" { Text "H:/03-源碼文件/VHDL/03-數(shù)字鐘/leddrv.vhd" 38 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 leddrv " "Info: Found entity 1: leddrv" {  } { { "leddrv.vhd" "" { Text "H:/03-源碼文件/VHDL/03-數(shù)字鐘/leddrv.vhd" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "choice1from6.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file choice1from6.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 choice1from6-choice1from6_architecture " "Info: Found design unit 1: choice1from6-choice1from6_architecture" {  } { { "choice1from6.vhd" "" { Text "H:/03-源碼文件/VHDL/03-數(shù)字鐘/choice1from6.vhd" 67 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 choice1from6 " "Info: Found entity 1: choice1from6" {  } { { "choice1from6.vhd" "" { Text "H:/03-源碼文件/VHDL/03-數(shù)字鐘/choice1from6.vhd" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg7_leddrv.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file seg7_leddrv.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seg7_leddrv-seg7_leddrv_architecture " "Info: Found design unit 1: seg7_leddrv-seg7_leddrv_architecture" {  } { { "seg7_leddrv.vhd" "" { Text "H:/03-源碼文件/VHDL/03-數(shù)字鐘/seg7_leddrv.vhd" 44 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 seg7_leddrv " "Info: Found entity 1: seg7_leddrv" {  } { { "seg7_leddrv.vhd" "" { Text "H:/03-源碼文件/VHDL/03-數(shù)字鐘/seg7_leddrv.vhd" 33 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DigitalClock.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file DigitalClock.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 DigitalClock " "Info: Found entity 1: DigitalClock" {  } { { "DigitalClock.bdf" "" { Schematic "H:/03-源碼文件/VHDL/03-數(shù)字鐘/DigitalClock.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DigitalClock " "Info: Elaborating entity \"DigitalClock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "carrier counter inst " "Warning: Port \"carrier\" of type counter and instance \"inst\" is missing source signal" {  } { { "DigitalClock.bdf" "" { Schematic "H:/03-源碼文件/VHDL/03-數(shù)字鐘/DigitalClock.bdf" { { -88 192 336 8 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "counter counter inst " "Warning: Port \"counter\" of type counter and instance \"inst\" is missing source signal" {  } { { "DigitalClock.bdf" "" { Schematic "H:/03-源碼文件/VHDL/03-數(shù)字鐘/DigitalClock.bdf" { { -88 192 336 8 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "carrier counter inst11 " "Warning: Port \"carrier\" of type counter and instance \"inst11\" is missing source signal" {  } { { "DigitalClock.bdf" "" { Schematic "H:/03-源碼文件/VHDL/03-數(shù)字鐘/DigitalClock.bdf" { { 32 192 336 128 "inst11" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "counter counter inst11 " "Warning: Port \"counter\" of type counter and instance \"inst11\" is missing source signal" {  } { { "DigitalClock.bdf" "" { Schematic "H:/03-源碼文件/VHDL/03-數(shù)字鐘/DigitalClock.bdf" { { 32 192 336 128 "inst11" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "carrier counter inst1 " "Warning: Port \"carrier\" of type counter and instance \"inst1\" is missing source signal" {  } { { "DigitalClock.bdf" "" { Schematic "H:/03-源碼文件/VHDL/03-數(shù)字鐘/DigitalClock.bdf" { { 152 192 336 248 "inst1" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "counter counter inst1 " "Warning: Port \"counter\" of type counter and instance \"inst1\" is missing source signal" {  } { { "DigitalClock.bdf" "" { Schematic "H:/03-源碼文件/VHDL/03-數(shù)字鐘/DigitalClock.bdf" { { 152 192 336 248 "inst1" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "carrier counter inst2 " "Warning: Port \"carrier\" of type counter and instance \"inst2\" is missing source signal" {  } { { "DigitalClock.bdf" "" { Schematic "H:/03-源碼文件/VHDL/03-數(shù)字鐘/DigitalClock.bdf" { { 272 192 336 368 "inst2" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "counter counter inst2 " "Warning: Port \"counter\" of type counter and instance \"inst2\" is missing source signal" {  } { { "DigitalClock.bdf" "" { Schematic "H:/03-源碼文件/VHDL/03-數(shù)字鐘/DigitalClock.bdf" { { 272 192 336 368 "inst2" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "carrier counter inst3 " "Warning: Port \"carrier\" of type counter and instance \"inst3\" is missing source signal" {  } { { "DigitalClock.bdf" "" { Schematic "H:/03-源碼文件/VHDL/03-數(shù)字鐘/DigitalClock.bdf" { { 392 192 336 488 "inst3" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "counter counter inst3 " "Warning: Port \"counter\" of type counter and instance \"inst3\" is missing source signal" {  } { { "DigitalClock.bdf" "" { Schematic "H:/03-源碼文件/VHDL/03-數(shù)字鐘/DigitalClock.bdf" { { 392 192 336 488 "inst3" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "carrier counter inst4 " "Warning: Port \"carrier\" of type counter and instance \"inst4\" is missing source signal" {  } { { "DigitalClock.bdf" "" { Schematic "H:/03-源碼文件/VHDL/03-數(shù)字鐘/DigitalClock.bdf" { { 512 192 336 608 "inst4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "counter counter inst4 " "Warning: Port \"counter\" of type counter and instance \"inst4\" is missing source signal" {  } { { "DigitalClock.bdf" "" { Schematic "H:/03-源碼文件/VHDL/03-數(shù)字鐘/DigitalClock.bdf" { { 512 192 336 608 "inst4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "carrier counter inst5 " "Warning: Port \"carrier\" of type counter and instance \"inst5\" is missing source signal" {  } { { "DigitalClock.bdf" "" { Schematic "H:/03-源碼文件/VHDL/03-數(shù)字鐘/DigitalClock.bdf" { { 632 192 336 728 "inst5" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "counter counter inst5 " "Warning: Port \"counter\" of type counter and instance \"inst5\" is missing source signal" {  } { { "DigitalClock.bdf" "" { Schematic "H:/03-源碼文件/VHDL/03-數(shù)字鐘/DigitalClock.bdf" { { 632 192 336 728 "inst5" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "carrier counter inst7 " "Warning: Port \"carrier\" of type counter and instance \"inst7\" is missing source signal" {  } { { "DigitalClock.bdf" "" { Schematic "H:/03-源碼文件/VHDL/03-數(shù)字鐘/DigitalClock.bdf" { { 752 192 336 848 "inst7" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "counter counter inst7 " "Warning: Port \"counter\" of type counter and instance \"inst7\" is missing source signal" {  } { { "DigitalClock.bdf" "" { Schematic "H:/03-源碼文件/VHDL/03-數(shù)字鐘/DigitalClock.bdf" { { 752 192 336 848 "inst7" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}