?? digital6counter.hier_info
字號:
|DigitalClock
led_bits[0] <= leddrv:inst10.led_bits[0]
led_bits[1] <= leddrv:inst10.led_bits[1]
led_bits[2] <= leddrv:inst10.led_bits[2]
led_bits[3] <= leddrv:inst10.led_bits[3]
led_bits[4] <= leddrv:inst10.led_bits[4]
led_bits[5] <= leddrv:inst10.led_bits[5]
led_bits[6] <= leddrv:inst10.led_bits[6]
led_bits[7] <= leddrv:inst10.led_bits[7]
reset => leddrv:inst10.reset
reset => counter:inst.reset
reset => counter:inst11.reset
reset => counter:inst1.reset
reset => choice1from6:inst8.reset
reset => counter:inst2.reset
reset => counter:inst3.reset
reset => counter:inst4.reset
reset => counter:inst5.reset
reset => counter:inst7.reset
reset => counter:inst6.reset
reset => seg7_leddrv:inst9.reset
clock => counter:inst.clock
led_cs[0] <= choice1from6:inst8.led_cs[0]
led_cs[1] <= choice1from6:inst8.led_cs[1]
led_cs[2] <= choice1from6:inst8.led_cs[2]
led_cs[3] <= choice1from6:inst8.led_cs[3]
led_cs[4] <= choice1from6:inst8.led_cs[4]
led_cs[5] <= choice1from6:inst8.led_cs[5]
seg7led_bits[0] <= seg7_leddrv:inst9.seg7led_bits[0]
seg7led_bits[1] <= seg7_leddrv:inst9.seg7led_bits[1]
seg7led_bits[2] <= seg7_leddrv:inst9.seg7led_bits[2]
seg7led_bits[3] <= seg7_leddrv:inst9.seg7led_bits[3]
seg7led_bits[4] <= seg7_leddrv:inst9.seg7led_bits[4]
seg7led_bits[5] <= seg7_leddrv:inst9.seg7led_bits[5]
seg7led_bits[6] <= seg7_leddrv:inst9.seg7led_bits[6]
seg7led_bits[7] <= seg7_leddrv:inst9.seg7led_bits[7]
|DigitalClock|leddrv:inst10
data[0] => Mux~1.IN19
data[0] => Mux~2.IN19
data[0] => Mux~3.IN19
data[0] => Mux~4.IN19
data[0] => Mux~5.IN19
data[0] => Mux~6.IN19
data[0] => Mux~7.IN10
data[1] => Mux~0.IN10
data[1] => Mux~1.IN18
data[1] => Mux~2.IN18
data[1] => Mux~3.IN18
data[1] => Mux~4.IN18
data[1] => Mux~5.IN18
data[1] => Mux~6.IN18
data[1] => Mux~7.IN9
data[2] => Mux~0.IN9
data[2] => Mux~1.IN17
data[2] => Mux~2.IN17
data[2] => Mux~3.IN17
data[2] => Mux~4.IN17
data[2] => Mux~5.IN17
data[2] => Mux~6.IN17
data[2] => Mux~7.IN8
data[3] => Mux~0.IN8
data[3] => Mux~1.IN16
data[3] => Mux~2.IN16
data[3] => Mux~3.IN16
data[3] => Mux~4.IN16
data[3] => Mux~5.IN16
data[3] => Mux~6.IN16
reset => process0~0.IN0
led_bits[0] <= led_bits~7.DB_MAX_OUTPUT_PORT_TYPE
led_bits[1] <= led_bits~6.DB_MAX_OUTPUT_PORT_TYPE
led_bits[2] <= led_bits~5.DB_MAX_OUTPUT_PORT_TYPE
led_bits[3] <= led_bits~4.DB_MAX_OUTPUT_PORT_TYPE
led_bits[4] <= led_bits~3.DB_MAX_OUTPUT_PORT_TYPE
led_bits[5] <= led_bits~2.DB_MAX_OUTPUT_PORT_TYPE
led_bits[6] <= led_bits~1.DB_MAX_OUTPUT_PORT_TYPE
led_bits[7] <= led_bits~0.DB_MAX_OUTPUT_PORT_TYPE
|DigitalClock|counter:inst1
clock => delay_counter[3].CLK
clock => delay_counter[2].CLK
clock => delay_counter[1].CLK
clock => delay_counter[0].CLK
clock => counter[3]~reg0.CLK
clock => counter[2]~reg0.CLK
clock => counter[1]~reg0.CLK
clock => counter[0]~reg0.CLK
clock => carrier~reg0.CLK
reset => process0~0.IN0
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
carrier <= carrier~reg0.DB_MAX_OUTPUT_PORT_TYPE
|DigitalClock|counter:inst11
clock => delay_counter[6].CLK
clock => delay_counter[5].CLK
clock => delay_counter[4].CLK
clock => delay_counter[3].CLK
clock => delay_counter[2].CLK
clock => delay_counter[1].CLK
clock => delay_counter[0].CLK
clock => counter[3]~reg0.CLK
clock => counter[2]~reg0.CLK
clock => counter[1]~reg0.CLK
clock => counter[0]~reg0.CLK
clock => carrier~reg0.CLK
reset => process0~0.IN0
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
carrier <= carrier~reg0.DB_MAX_OUTPUT_PORT_TYPE
|DigitalClock|counter:inst
clock => delay_counter[14].CLK
clock => delay_counter[13].CLK
clock => delay_counter[12].CLK
clock => delay_counter[11].CLK
clock => delay_counter[10].CLK
clock => delay_counter[9].CLK
clock => delay_counter[8].CLK
clock => delay_counter[7].CLK
clock => delay_counter[6].CLK
clock => delay_counter[5].CLK
clock => delay_counter[4].CLK
clock => delay_counter[3].CLK
clock => delay_counter[2].CLK
clock => delay_counter[1].CLK
clock => delay_counter[0].CLK
clock => counter[3]~reg0.CLK
clock => counter[2]~reg0.CLK
clock => counter[1]~reg0.CLK
clock => counter[0]~reg0.CLK
clock => carrier~reg0.CLK
reset => process0~0.IN0
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
carrier <= carrier~reg0.DB_MAX_OUTPUT_PORT_TYPE
|DigitalClock|choice1from6:inst8
led_bits[0] <= led_bits[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
led_bits[1] <= led_bits[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
led_bits[2] <= led_bits[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
led_bits[3] <= led_bits[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
led_cs[0] <= led_cs[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
led_cs[1] <= led_cs[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
led_cs[2] <= led_cs[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
led_cs[3] <= led_cs[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
led_cs[4] <= led_cs[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
led_cs[5] <= led_cs[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dp <= dp~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_in0[0] => Mux~3.IN58
data_in0[1] => Mux~2.IN58
data_in0[2] => Mux~1.IN58
data_in0[3] => Mux~0.IN58
data_in1[0] => Mux~3.IN59
data_in1[1] => Mux~2.IN59
data_in1[2] => Mux~1.IN59
data_in1[3] => Mux~0.IN59
data_in2[0] => Mux~3.IN60
data_in2[1] => Mux~2.IN60
data_in2[2] => Mux~1.IN60
data_in2[3] => Mux~0.IN60
data_in3[0] => Mux~3.IN61
data_in3[1] => Mux~2.IN61
data_in3[2] => Mux~1.IN61
data_in3[3] => Mux~0.IN61
data_in4[1] => Mux~2.IN62
data_in4[2] => Mux~1.IN62
data_in4[3] => Mux~0.IN62
data_in5[0] => Mux~3.IN63
data_in5[1] => Mux~2.IN63
data_in5[2] => Mux~1.IN63
data_in5[3] => Mux~0.IN63
clk => led_cs[4]~reg0.CLK
clk => led_cs[3]~reg0.CLK
clk => led_cs[2]~reg0.CLK
clk => led_cs[1]~reg0.CLK
clk => led_cs[0]~reg0.CLK
clk => dp~reg0.CLK
clk => led_bits[3]~reg0.CLK
clk => led_bits[2]~reg0.CLK
clk => led_bits[1]~reg0.CLK
clk => led_bits[0]~reg0.CLK
clk => next_led_cs[5].CLK
clk => next_led_cs[4].CLK
clk => next_led_cs[3].CLK
clk => next_led_cs[2].CLK
clk => next_led_cs[1].CLK
clk => next_led_cs[0].CLK
clk => led_cs[5]~reg0.CLK
reset => process0~0.IN0
|DigitalClock|counter:inst2
clock => delay_counter[3].CLK
clock => delay_counter[2].CLK
clock => delay_counter[1].CLK
clock => delay_counter[0].CLK
clock => counter[3]~reg0.CLK
clock => counter[2]~reg0.CLK
clock => counter[1]~reg0.CLK
clock => counter[0]~reg0.CLK
clock => carrier~reg0.CLK
reset => process0~0.IN0
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
carrier <= carrier~reg0.DB_MAX_OUTPUT_PORT_TYPE
|DigitalClock|counter:inst3
clock => delay_counter[2].CLK
clock => delay_counter[1].CLK
clock => delay_counter[0].CLK
clock => counter[3]~reg0.CLK
clock => counter[2]~reg0.CLK
clock => counter[1]~reg0.CLK
clock => counter[0]~reg0.CLK
clock => carrier~reg0.CLK
reset => process0~0.IN0
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
carrier <= carrier~reg0.DB_MAX_OUTPUT_PORT_TYPE
|DigitalClock|counter:inst4
clock => delay_counter[3].CLK
clock => delay_counter[2].CLK
clock => delay_counter[1].CLK
clock => delay_counter[0].CLK
clock => counter[3]~reg0.CLK
clock => counter[2]~reg0.CLK
clock => counter[1]~reg0.CLK
clock => counter[0]~reg0.CLK
clock => carrier~reg0.CLK
reset => process0~0.IN0
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
carrier <= carrier~reg0.DB_MAX_OUTPUT_PORT_TYPE
|DigitalClock|counter:inst5
clock => delay_counter[2].CLK
clock => delay_counter[1].CLK
clock => delay_counter[0].CLK
clock => counter[3]~reg0.CLK
clock => counter[2]~reg0.CLK
clock => counter[1]~reg0.CLK
clock => counter[0]~reg0.CLK
clock => carrier~reg0.CLK
reset => process0~0.IN0
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
carrier <= carrier~reg0.DB_MAX_OUTPUT_PORT_TYPE
|DigitalClock|counter:inst7
clock => delay_counter[3].CLK
clock => delay_counter[2].CLK
clock => delay_counter[1].CLK
clock => delay_counter[0].CLK
clock => counter[3]~reg0.CLK
clock => counter[2]~reg0.CLK
clock => counter[1]~reg0.CLK
clock => counter[0]~reg0.CLK
clock => carrier~reg0.CLK
reset => process0~0.IN0
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
carrier <= carrier~reg0.DB_MAX_OUTPUT_PORT_TYPE
|DigitalClock|counter:inst6
clock => delay_counter[3].CLK
clock => delay_counter[2].CLK
clock => delay_counter[1].CLK
clock => delay_counter[0].CLK
clock => counter[3]~reg0.CLK
clock => counter[2]~reg0.CLK
clock => counter[1]~reg0.CLK
clock => counter[0]~reg0.CLK
clock => carrier~reg0.CLK
reset => process0~0.IN0
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
carrier <= carrier~reg0.DB_MAX_OUTPUT_PORT_TYPE
|DigitalClock|seg7_leddrv:inst9
seg7led_bits[0] <= seg7led_bits~7.DB_MAX_OUTPUT_PORT_TYPE
seg7led_bits[1] <= seg7led_bits~6.DB_MAX_OUTPUT_PORT_TYPE
seg7led_bits[2] <= seg7led_bits~5.DB_MAX_OUTPUT_PORT_TYPE
seg7led_bits[3] <= seg7led_bits~4.DB_MAX_OUTPUT_PORT_TYPE
seg7led_bits[4] <= seg7led_bits~3.DB_MAX_OUTPUT_PORT_TYPE
seg7led_bits[5] <= seg7led_bits~2.DB_MAX_OUTPUT_PORT_TYPE
seg7led_bits[6] <= seg7led_bits~1.DB_MAX_OUTPUT_PORT_TYPE
seg7led_bits[7] <= seg7led_bits~0.DB_MAX_OUTPUT_PORT_TYPE
data[0] => Mux~0.IN19
data[0] => Mux~1.IN19
data[0] => Mux~2.IN19
data[0] => Mux~3.IN19
data[0] => Mux~4.IN19
data[0] => Mux~5.IN19
data[0] => Mux~6.IN19
data[1] => Mux~0.IN18
data[1] => Mux~1.IN18
data[1] => Mux~2.IN18
data[1] => Mux~3.IN18
data[1] => Mux~4.IN18
data[1] => Mux~5.IN18
data[1] => Mux~6.IN18
data[2] => Mux~0.IN17
data[2] => Mux~1.IN17
data[2] => Mux~2.IN17
data[2] => Mux~3.IN17
data[2] => Mux~4.IN17
data[2] => Mux~5.IN17
data[2] => Mux~6.IN17
data[3] => Mux~0.IN16
data[3] => Mux~1.IN16
data[3] => Mux~2.IN16
data[3] => Mux~3.IN16
data[3] => Mux~4.IN16
data[3] => Mux~5.IN16
data[3] => Mux~6.IN16
dp => seg7led_bits~0.DATAA
reset => process0~0.IN0
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