?? sram2.stp
字號:
<net is_signal_inverted="no" name="tmp_data[8]"/>
<net is_signal_inverted="no" name="tmp_data[9]"/>
<net is_signal_inverted="no" name="tmp_data[10]"/>
<net is_signal_inverted="no" name="tmp_data[11]"/>
<net is_signal_inverted="no" name="tmp_data[12]"/>
<net is_signal_inverted="no" name="tmp_data[13]"/>
<net is_signal_inverted="no" name="tmp_data[14]"/>
<net is_signal_inverted="no" name="tmp_data[15]"/>
</bus>
<bus is_signal_inverted="no" link="all" name="tmp_addr" order="lsb_to_msb" radix="hex" state="collapse" type="register">
<net is_signal_inverted="no" name="tmp_addr[0]"/>
<net is_signal_inverted="no" name="tmp_addr[1]"/>
<net is_signal_inverted="no" name="tmp_addr[2]"/>
<net is_signal_inverted="no" name="tmp_addr[3]"/>
<net is_signal_inverted="no" name="tmp_addr[4]"/>
<net is_signal_inverted="no" name="tmp_addr[5]"/>
<net is_signal_inverted="no" name="tmp_addr[6]"/>
<net is_signal_inverted="no" name="tmp_addr[7]"/>
<net is_signal_inverted="no" name="tmp_addr[8]"/>
<net is_signal_inverted="no" name="tmp_addr[9]"/>
<net is_signal_inverted="no" name="tmp_addr[10]"/>
<net is_signal_inverted="no" name="tmp_addr[11]"/>
<net is_signal_inverted="no" name="tmp_addr[12]"/>
<net is_signal_inverted="no" name="tmp_addr[13]"/>
<net is_signal_inverted="no" name="tmp_addr[14]"/>
<net is_signal_inverted="no" name="tmp_addr[15]"/>
<net is_signal_inverted="no" name="tmp_addr[16]"/>
<net is_signal_inverted="no" name="tmp_addr[17]"/>
</bus>
<bus is_signal_inverted="no" link="all" name="SRAM_ADDR" order="lsb_to_msb" radix="hex" state="collapse" type="output pin">
<net is_signal_inverted="no" name="SRAM_ADDR[0]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[1]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[2]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[3]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[4]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[5]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[6]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[7]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[8]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[9]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[10]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[11]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[12]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[13]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[14]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[15]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[16]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[17]"/>
</bus>
<bus is_signal_inverted="no" link="all" name="SRAM_DQ" order="lsb_to_msb" radix="hex" state="collapse" type="bidir pin">
<net is_signal_inverted="no" name="SRAM_DQ[0]"/>
<net is_signal_inverted="no" name="SRAM_DQ[1]"/>
<net is_signal_inverted="no" name="SRAM_DQ[2]"/>
<net is_signal_inverted="no" name="SRAM_DQ[3]"/>
<net is_signal_inverted="no" name="SRAM_DQ[4]"/>
<net is_signal_inverted="no" name="SRAM_DQ[5]"/>
<net is_signal_inverted="no" name="SRAM_DQ[6]"/>
<net is_signal_inverted="no" name="SRAM_DQ[7]"/>
<net is_signal_inverted="no" name="SRAM_DQ[8]"/>
<net is_signal_inverted="no" name="SRAM_DQ[9]"/>
<net is_signal_inverted="no" name="SRAM_DQ[10]"/>
<net is_signal_inverted="no" name="SRAM_DQ[11]"/>
<net is_signal_inverted="no" name="SRAM_DQ[12]"/>
<net is_signal_inverted="no" name="SRAM_DQ[13]"/>
<net is_signal_inverted="no" name="SRAM_DQ[14]"/>
<net is_signal_inverted="no" name="SRAM_DQ[15]"/>
</bus>
<bus is_signal_inverted="no" link="all" name="data_out" order="lsb_to_msb" radix="hex" state="collapse" type="output pin">
<net is_signal_inverted="no" name="data_out[0]"/>
<net is_signal_inverted="no" name="data_out[1]"/>
<net is_signal_inverted="no" name="data_out[2]"/>
<net is_signal_inverted="no" name="data_out[3]"/>
<net is_signal_inverted="no" name="data_out[4]"/>
<net is_signal_inverted="no" name="data_out[5]"/>
<net is_signal_inverted="no" name="data_out[6]"/>
<net is_signal_inverted="no" name="data_out[7]"/>
<net is_signal_inverted="no" name="data_out[8]"/>
<net is_signal_inverted="no" name="data_out[9]"/>
<net is_signal_inverted="no" name="data_out[10]"/>
<net is_signal_inverted="no" name="data_out[11]"/>
<net is_signal_inverted="no" name="data_out[12]"/>
<net is_signal_inverted="no" name="data_out[13]"/>
<net is_signal_inverted="no" name="data_out[14]"/>
<net is_signal_inverted="no" name="data_out[15]"/>
</bus>
</data_view>
<setup_view>
<bus is_signal_inverted="no" link="all" name="tmp_data" order="lsb_to_msb" radix="hex" state="collapse" type="register">
<net is_signal_inverted="no" name="tmp_data[0]"/>
<net is_signal_inverted="no" name="tmp_data[1]"/>
<net is_signal_inverted="no" name="tmp_data[2]"/>
<net is_signal_inverted="no" name="tmp_data[3]"/>
<net is_signal_inverted="no" name="tmp_data[4]"/>
<net is_signal_inverted="no" name="tmp_data[5]"/>
<net is_signal_inverted="no" name="tmp_data[6]"/>
<net is_signal_inverted="no" name="tmp_data[7]"/>
<net is_signal_inverted="no" name="tmp_data[8]"/>
<net is_signal_inverted="no" name="tmp_data[9]"/>
<net is_signal_inverted="no" name="tmp_data[10]"/>
<net is_signal_inverted="no" name="tmp_data[11]"/>
<net is_signal_inverted="no" name="tmp_data[12]"/>
<net is_signal_inverted="no" name="tmp_data[13]"/>
<net is_signal_inverted="no" name="tmp_data[14]"/>
<net is_signal_inverted="no" name="tmp_data[15]"/>
</bus>
<bus is_signal_inverted="no" link="all" name="tmp_addr" order="lsb_to_msb" radix="hex" state="collapse" type="register">
<net is_signal_inverted="no" name="tmp_addr[0]"/>
<net is_signal_inverted="no" name="tmp_addr[1]"/>
<net is_signal_inverted="no" name="tmp_addr[2]"/>
<net is_signal_inverted="no" name="tmp_addr[3]"/>
<net is_signal_inverted="no" name="tmp_addr[4]"/>
<net is_signal_inverted="no" name="tmp_addr[5]"/>
<net is_signal_inverted="no" name="tmp_addr[6]"/>
<net is_signal_inverted="no" name="tmp_addr[7]"/>
<net is_signal_inverted="no" name="tmp_addr[8]"/>
<net is_signal_inverted="no" name="tmp_addr[9]"/>
<net is_signal_inverted="no" name="tmp_addr[10]"/>
<net is_signal_inverted="no" name="tmp_addr[11]"/>
<net is_signal_inverted="no" name="tmp_addr[12]"/>
<net is_signal_inverted="no" name="tmp_addr[13]"/>
<net is_signal_inverted="no" name="tmp_addr[14]"/>
<net is_signal_inverted="no" name="tmp_addr[15]"/>
<net is_signal_inverted="no" name="tmp_addr[16]"/>
<net is_signal_inverted="no" name="tmp_addr[17]"/>
</bus>
<bus is_signal_inverted="no" link="all" name="SRAM_ADDR" order="lsb_to_msb" radix="hex" state="collapse" type="output pin">
<net is_signal_inverted="no" name="SRAM_ADDR[0]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[1]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[2]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[3]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[4]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[5]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[6]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[7]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[8]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[9]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[10]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[11]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[12]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[13]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[14]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[15]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[16]"/>
<net is_signal_inverted="no" name="SRAM_ADDR[17]"/>
</bus>
<bus is_signal_inverted="no" link="all" name="SRAM_DQ" order="lsb_to_msb" radix="hex" state="collapse" type="bidir pin">
<net is_signal_inverted="no" name="SRAM_DQ[0]"/>
<net is_signal_inverted="no" name="SRAM_DQ[1]"/>
<net is_signal_inverted="no" name="SRAM_DQ[2]"/>
<net is_signal_inverted="no" name="SRAM_DQ[3]"/>
<net is_signal_inverted="no" name="SRAM_DQ[4]"/>
<net is_signal_inverted="no" name="SRAM_DQ[5]"/>
<net is_signal_inverted="no" name="SRAM_DQ[6]"/>
<net is_signal_inverted="no" name="SRAM_DQ[7]"/>
<net is_signal_inverted="no" name="SRAM_DQ[8]"/>
<net is_signal_inverted="no" name="SRAM_DQ[9]"/>
<net is_signal_inverted="no" name="SRAM_DQ[10]"/>
<net is_signal_inverted="no" name="SRAM_DQ[11]"/>
<net is_signal_inverted="no" name="SRAM_DQ[12]"/>
<net is_signal_inverted="no" name="SRAM_DQ[13]"/>
<net is_signal_inverted="no" name="SRAM_DQ[14]"/>
<net is_signal_inverted="no" name="SRAM_DQ[15]"/>
</bus>
<bus is_signal_inverted="no" link="all" name="data_out" order="lsb_to_msb" radix="hex" state="collapse" type="output pin">
<net is_signal_inverted="no" name="data_out[0]"/>
<net is_signal_inverted="no" name="data_out[1]"/>
<net is_signal_inverted="no" name="data_out[2]"/>
<net is_signal_inverted="no" name="data_out[3]"/>
<net is_signal_inverted="no" name="data_out[4]"/>
<net is_signal_inverted="no" name="data_out[5]"/>
<net is_signal_inverted="no" name="data_out[6]"/>
<net is_signal_inverted="no" name="data_out[7]"/>
<net is_signal_inverted="no" name="data_out[8]"/>
<net is_signal_inverted="no" name="data_out[9]"/>
<net is_signal_inverted="no" name="data_out[10]"/>
<net is_signal_inverted="no" name="data_out[11]"/>
<net is_signal_inverted="no" name="data_out[12]"/>
<net is_signal_inverted="no" name="data_out[13]"/>
<net is_signal_inverted="no" name="data_out[14]"/>
<net is_signal_inverted="no" name="data_out[15]"/>
</bus>
</setup_view>
</presentation>
<trigger global_temp="1" name="trigger: 2008/06/02 16:32:13 #1" position="pre" power_up_trigger_mode="false" segment_size="1" trigger_in="dont_care" trigger_out="active high" trigger_type="circular">
<power_up_trigger position="pre" segment_size="1" trigger_in="dont_care" trigger_out="active high" trigger_type="circular"/>
<events>
<level enabled="yes" type="basic">
<power_up enabled="yes">
</power_up>
<op_node/>
</level>
</events>
</trigger>
</signal_set>
</instance>
<mnemonics/>
<static_plugin_mnemonics/>
<global_info>
<single attribute="active instance" value="0"/>
<single attribute="lock mode" value="36110"/>
<multi attribute="window position" size="9" value="803,481,398,124,356,50,32,0,1"/>
</global_info>
</session>
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