library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity x_detect is
port(data,clk:in std_logic;
           y:  out std_logic);
end x_detect;
architecture behav of x_detect is
type state is(s1,s2,s3,s4,s5,s6,s7,s8);
signal p: state;
signal n:state;
begin
process(clk)
begin
if clk'event and clk='1' then
p<=n;
end if;
end process;
process(data,p)
begin
case p is
when s1=>if data='1' then
     n<=s2;
   else
     n<=s1;
     end if;
y<='0';
when s2=>if data='1' then
     n<=s3;
   else
     n<=s1;
     end if;
y<='0'; 
 
when s3=>if data='1' then
     n<=s4;
   else
     n<=s1;
     end if;
y<='0';
when s4=>if data='0' then
     n<=s5;
   else
     n<=s4;
     end if;
y<='0';
when s5=>if data='0' then
     n<=s6;
   else
     n<=s2;
     end if;
y<='0';
when s6=>if data='1' then
     n<=s7;
   else
     n<=s1;
     end if;
y<='0';
when s7=>if data='0' then
     n<=s8;
   else
     n<=s3;
     end if;
y<='0';
when s8=>if data='0' then
     n<=s1;
   else
     n<=s2;
     end if;
y<='1'; 
when others=>null;
end case;
end process;
end behav;