library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity frame is
    Port ( clk : in std_logic;
           reset : in std_logic;
           hcnt : in std_logic_vector(9 downto 0);
           vcnt : in std_logic_vector(9 downto 0);
           backcolor : out std_logic_vector(7 downto 0));
end frame;

architecture Behavioral of frame is

CONSTANT FRAME_WIDTH : INTEGER :=20;

signal frameout : std_logic_vector(7 downto 0);

begin

XX: process(clk,hcnt,vcnt,reset)
begin
  if (reset='0') then
    frameout <= "00000000";
  elsif (clk'event and clk='1') then
		--if ((hcnt>=0 and hcnt<=19) or (hcnt>=780 and hcnt<=799) or
	    --   (vcnt>=0 and vcnt<=19) or (vcnt>=580 and vcnt<=599)) then
		if ((hcnt>=0 and hcnt<=(FRAME_WIDTH-1)) and (vcnt>=0 and vcnt<=479)) or
		   ((hcnt>=(640-FRAME_WIDTH) and hcnt<=639) and (vcnt>=0 and vcnt<=479)) or
			((hcnt>=0 and hcnt<=639) and (vcnt>=0 and vcnt<=(FRAME_WIDTH-1))) or
			((hcnt>=0 and hcnt<=639) and (vcnt>=(480-FRAME_WIDTH) and vcnt<=479)) then
	 	  frameout <= "11000000";
		else
		   frameout <= "00000000";
		end if;
 end if;
end process;

backcolor <= frameout;

end Behavioral;