------------------------------------------------------------------------------------ Company: -- Engineer: -- -- Create Date:    11:20:25 06/09/2008 -- Design Name: -- Module Name:    drawclock - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity drawclock is    Port ( clk : in std_logic;           reset : in std_logic;			  hcnt : in std_logic_vector(9 downto 0);           vcnt : in std_logic_vector(9 downto 0);           location : in std_logic_vector(9 downto 0);           boardrgb : out std_logic_vector(7 downto 0));end drawclock;architecture Behavioral of drawclock isCONSTANT FRAME_WIDTH : INTEGER :=20;CONSTANT BOARD_WIDTH : INTEGER :=20;CONSTANT BOARD_LEN : INTEGER :=30;--THIE IS THE 1/2 LENGTH OF BOARDsignal rgbout : std_logic_vector(7 downto 0);begin  drawclock: process(reset,clk,hcnt,vcnt)  begin    if reset='0' then	   rgbout <= "00000000";	 elsif (clk'event and clk='1') then	   if ((hcnt>(location-BOARD_LEN)) and (hcnt<(location+BOARD_LEN)) and (vcnt>=(480-FRAME_WIDTH-BOARD_WIDTH)) and (vcnt<=(479-FRAME_WIDTH))) then			rgbout <="00111000";		 else		   rgbout <= "00000000";		 end if;	  end if;	end process;   boardrgb <= rgbout;end Behavioral;