library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity clock is    Port ( clk : in std_logic;           reset : in std_logic;			  hcnt : in std_logic_vector(9 downto 0);           vcnt : in std_logic_vector(9 downto 0);           location : in std_logic_vector(9 downto 0);           boardrgb : out std_logic_vector(7 downto 0));end board;architecture Behavioral of board isCONSTANT FRAME_WIDTH : INTEGER :=20;CONSTANT BOARD_WIDTH : INTEGER :=20;CONSTANT BOARD_LEN : INTEGER :=30;--THIE IS THE 1/2 LENGTH OF BOARDsignal rgbout : std_logic_vector(7 downto 0);begin  drawboard: process(reset,clk,hcnt,vcnt)  begin    if reset='0' then	   rgbout <= "00000000";	 elsif (clk'event and clk='1') then	   if ((hcnt>(location-BOARD_LEN)) and (hcnt<(location+BOARD_LEN)) and (vcnt>=(480-FRAME_WIDTH-BOARD_WIDTH)) and (vcnt<=(479-FRAME_WIDTH))) then			rgbout <="00111000";		 else		   rgbout <= "00000000";		 end if;	  end if;	end process;   boardrgb <= rgbout;end Behavioral;