Fitter report for phase_test
Sun Aug 19 20:49:06 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. I/O Bank Usage
  9. All Package Pins
 10. PLL Summary
 11. PLL Usage
 12. Output Pin Default Load For Reported TCO
 13. Fitter Resource Utilization by Entity
 14. Delay Chain Summary
 15. Pad To Core Delay Chain Fanout
 16. Control Signals
 17. Global & Other Fast Signals
 18. Non-Global High Fan-Out Signals
 19. Interconnect Usage Summary
 20. LAB Logic Elements
 21. LAB-wide Signals
 22. LAB Signals Sourced
 23. LAB Signals Sourced Out
 24. LAB Distinct Inputs
 25. Fitter Device Options
 26. Fitter Messages
 27. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Successful - Sun Aug 19 20:49:06 2007    ;
; Quartus II Version    ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name         ; phase_test                               ;
; Top-level Entity Name ; phase_control                            ;
; Family                ; Cyclone                                  ;
; Device                ; EP1C6Q240C8                              ;
; Timing Models         ; Final                                    ;
; Total logic elements  ; 118 / 5,980 ( 2 % )                      ;
; Total pins            ; 54 / 185 ( 29 % )                        ;
; Total virtual pins    ; 0                                        ;
; Total memory bits     ; 0 / 92,160 ( 0 % )                       ;
; Total PLLs            ; 1 / 2 ( 50 % )                           ;
+-----------------------+------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                      ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Option                                             ; Setting                        ; Default Value                  ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Device                                             ; EP1C6Q240C8                    ;                                ;
; Use smart compilation                              ; Off                            ; Off                            ;
; Router Timing Optimization Level                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                        ; Off                            ; Off                            ;
; Optimize Timing                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing         ; On                             ; On                             ;
; Limit to One Fitting Attempt                       ; Off                            ; Off                            ;