library ieee;--------8 bits serial input parallel output
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sipo is
  port (d_in:in std_logic;
        clk :in std_logic;
        d_out:out std_logic_vector(7 downto 0));
end sipo;
architecture a of sipo is
  signal q: std_logic_vector(7 downto 0);
begin 
  process(clk)
  begin 
    if clk 'event and clk='1'then 
     q(0)<=d_in;
     for i in 1 to 7 loop
       q(i)<=q(i-1);
     end loop;
    end if;
  end process;
  d_out<=q;
end a;