?? counter_tc_ce.v
字號:
//********************************************************
// Filename: counter_tc_ce.v
//
// Parameterized counter module with sync reset,
// clock enable, and terminal count.
//********************************************************
module counter_tc_ce(clk, reset, enable, q, tc);
parameter N = 8; // number of bits
parameter TCNT = 256; // desired terminal count
input clk, reset, enable;
output tc;
reg tc;
output [N-1:0] q;
reg [N-1:0] q;
// check for one less than what you want ...
wire tc_tmp;
assign tc_tmp = (q==TCNT-2);
// ... then register (causes 1-cycle delay)
always @(posedge clk)
if (reset) tc <= 0;
else tc <= tc_tmp;
// counter
always @(posedge clk)
if (reset) q <= 0;
else if (enable)
begin
if (tc) q <= 0;
else q <= q + 1;
end
endmodule
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