Fitter report for sditest
Thu Jun 12 17:56:06 2008
Quartus II Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. I/O Bank Usage
  9. All Package Pins
 10. Output Pin Default Load For Reported TCO
 11. Fitter Resource Utilization by Entity
 12. Delay Chain Summary
 13. Pad To Core Delay Chain Fanout
 14. Non-Global High Fan-Out Signals
 15. Interconnect Usage Summary
 16. Fitter Device Options
 17. Operating Settings and Conditions
 18. Advanced Data - General
 19. Advanced Data - Placement Preparation
 20. Advanced Data - Placement
 21. Advanced Data - Routing
 22. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Fitter Summary                                                                     ;
+------------------------------------+-----------------------------------------------+
; Fitter Status                      ; Successful - Thu Jun 12 17:56:06 2008         ;
; Quartus II Version                 ; 7.2 Build 203 02/05/2008 SP 2 SJ Full Version ;
; Revision Name                      ; sditest                                       ;
; Top-level Entity Name              ; sditest                                       ;
; Family                             ; Cyclone III                                   ;
; Device                             ; EP3C25F324C8                                  ;
; Timing Models                      ; Final                                         ;
; Total logic elements               ; 0 / 24,624 ( 0 % )                            ;
;     Total combinational functions  ; 0 / 24,624 ( 0 % )                            ;
;     Dedicated logic registers      ; 0 / 24,624 ( 0 % )                            ;
; Total registers                    ; 0                                             ;
; Total pins                         ; 4 / 216 ( 2 % )                               ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 0 / 608,256 ( 0 % )                           ;
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % )                               ;
; Total PLLs                         ; 0 / 4 ( 0 % )                                 ;
+------------------------------------+-----------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                                       ;
+-----------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Option                                                                ; Setting                               ; Default Value                         ;
+-----------------------------------------------------------------------+---------------------------------------+---------------------------------------+
; Device                                                                ; EP3C25F324C8                          ;                                       ;
; Use TimeQuest Timing Analyzer                                         ; On                                    ; Off                                   ;
; Minimum Core Junction Temperature                                     ; 0                                     ;                                       ;
; Maximum Core Junction Temperature                                     ; 85                                    ;                                       ;
; Fit Attempts to Skip                                                  ; 0                                     ; 0.0                                   ;
; Fitter Effort                                                         ; Standard Fit                          ; Auto Fit                              ;
; Use smart compilation                                                 ; Off                                   ; Off                                   ;
; Maximum processors allowed for parallel compilation                   ; 1                                     ; 1                                     ;
; Router Timing Optimization Level                                      ; Normal                                ; Normal                                ;
; Placement Effort Multiplier                                           ; 1.0                                   ; 1.0                                   ;
; Router Effort Multiplier                                              ; 1.0                                   ; 1.0                                   ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths        ; IO Paths and Minimum TPD Paths        ;