--*****************************************************************************
--* *
--* EuCore PCI-T32 - PCI Target Interface Core *
--* (C)2000 MaxLock, Inc. All rights reserved *
--* *
--*****************************************************************************
-- FILE : PCI_CMDADR.vhd
-- DATE : 10.1.2001
-- REVISION: 1.1
-- DESIGNER: Tony
-- Descr : PCI Command Decoder and Address Counter
-- Entities: PCI_CMDADR
-- Changes :
-- ******************************************************
-- * Entities *
-- ******************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all; -- Arithmetic operators
library WORK;
use WORK.PCI_COMMANDS.all;
entity PCI_CMDADR is
port(
RESET : in std_logic;
CLK : in std_logic;
DIN : in std_logic_vector(31 downto 0);
CBEnid : in std_logic_vector(3 downto 0);
IDSELd : in std_logic;
FRAMEnd : in std_logic;
ACC_END : in std_logic;
CFG_IOEN : in std_logic; -- I/O Space Decoding Enabled
CFG_MEMEN : in std_logic; -- Memory Space Decoding Enabled
INC_ADR : in std_logic; -- Incement Address Counter
-- System Control
FIRST_CYC : out std_logic; -- First Cycle After FRAME# falling edge
-- Captured Address
ADR : out std_logic_vector(31 downto 0); -- Captured address
BURST_MODE : out std_logic_vector(1 downto 0);--
-- Decoded Commands:
COMMAND : out std_logic_vector(3 downto 0);-- Binary encoded command
CMD_CFGRD : out std_logic; -- Configuration Read
CMD_CFGWR : out std_logic; -- Configuration Write
CMD_IORD : out std_logic; -- I/O Read
CMD_IOWR : out std_logic; -- I/O Write
CMD_MRD : out std_logic; -- Memory Read
CMD_MWR : out std_logic; -- Memory Write
CMD_MRM : out std_logic; -- Memory Read Multiple
CMD_MRL : out std_logic; -- Memory Read Line
CMD_MWI : out std_logic; -- Memory Write and Invalidate
-- 
ACC_CFG : out std_logic; -- Configuration Space Access
ACC_IO : out std_logic; -- I/O Space Access
ACC_MEM : out std_logic; -- Memory Space Access
ACC_WR : out std_logic; -- Card Write Access
ACC_RD : out std_logic -- Card Read Access
); end PCI_CMDADR;

-- ******************************************************
-- * Architectures *
-- ******************************************************
architecture RTL of PCI_CMDADR is

signal OldFrame, CycBegin : std_logic;
signal COMMANDi : std_logic_vector(3 downto 0);
signal ADRi,ADRi_New : std_logic_vector(31 downto 0);

begin
COMMAND <= COMMANDi;
ADR <= ADRi_New;
-- Remeber Previous value of FRAMEnd
OldFrm: process (CLK,RESET) is
begin
if (RESET = '1') then
OldFrame <= '1';
elsif (CLK'event and CLK='1') then
OldFrame <= FRAMEnd;
end if;
end process OldFrm;
-- Beginning od PCI access cycle detection
CycBegin <= OldFrame and not(FRAMEnd);
FIRST_CYC <= OldFrame and not(FRAMEnd);
-- CFG Space Access Decode
ACC_CFG <= '1' when (DIN(1 downto 0)="00") and (CBEnid(3 downto 1)="101")
and (IDSELd = '1') and (CycBegin ='1')
else '0';
-- I/O Space Access
ACC_IO <= '1' when (CFG_IOEN='1') and (CBEnid(3 downto 1)= "001")
else '0';
-- Memory Space Access
ACC_MEM <= '1' when (CFG_MEMEN='1') and (CBEnid(3 downto 1)= "011" or CBEnid(3 downto 1)= "111"
or CBEnid(3 downto 0)= "1100")
else '0';
-- 
RW_DEC: process(CLK,RESET)
begin
if (RESET = '1') then
ACC_RD <= '0';
ACC_WR <= '0';
elsif (CLK'event and CLK='1') then
if (ACC_END = '1') then
ACC_RD <= '0';
ACC_WR <= '0';
elsif (CycBegin = '1') then
ACC_RD <= not CBEnid(0);
ACC_WR <= CBEnid(0);
end if;
end if;
end process;
-- PCI Command Decoder
pCMD_DEC: process(CLK,RESET)
begin
if (RESET = '1') then
COMMANDi <= "1000";
CMD_CFGRD <= '0';
CMD_CFGWR <= '0';
CMD_IORD <= '0';
CMD_IOWR <= '0';
CMD_MRD <= '0';
CMD_MWR <= '0';
CMD_MRM <= '0';
CMD_MRL <= '0';
CMD_MWI <= '0';
BURST_MODE <= "00";
elsif (CLK'event and CLK='1') then
if (ACC_END = '1') then
COMMANDi <= "1000";
BURST_MODE <= "00";
CMD_CFGRD <= '0';
CMD_CFGWR <= '0';
CMD_IORD <= '0';
CMD_IOWR <= '0';
CMD_MRD <= '0';
CMD_MWR <= '0';
CMD_MRM <= '0';
CMD_MRL <= '0';
CMD_MWI <= '0';
elsif (CycBegin = '1') then
BURST_MODE <= DIN(1 downto 0);
COMMANDi <= CBEnid;
if CBEnid = CFGRD_CODE then -- Configuration Read
CMD_CFGRD <= '1';
else
CMD_CFGRD <= '0';
end if;
if CBEnid = CFGWR_CODE then -- Configuration Write
CMD_CFGWR <= '1';
else
CMD_CFGWR <= '0';
end if;
if CBEnid = IORD_CODE then -- I/O READ
CMD_IORD <= '1';
else
CMD_IORD <= '0';
end if;
if CBEnid = IOWR_CODE then -- I/O Write
CMD_IOWR <= '1';
else
CMD_IOWR <= '0';
end if;
if CBEnid = MRD_CODE then -- Memory Read
CMD_MRD <= '1';
else
CMD_MRD <= '0';
end if;
if CBEnid = MWR_CODE then -- Memory Write
CMD_MWR <= '1';
else
CMD_MWR <= '0';
end if;
if CBEnid = MRM_CODE then -- Memory Read Multiple
CMD_MRM <= '1';
else
CMD_MRM <= '0';
end if;
if CBEnid = MRL_CODE then -- Memory Read Line
CMD_MRL <= '1';
else
CMD_MRL <= '0';
end if;
if CBEnid = MWI_CODE then -- Memory Write and Invalidate
CMD_MWI <= '1';
else
CMD_MWI <= '0';
end if;
end if;
end if;
end process pCMD_DEC;
-- Address Counter
pADRCNT: process(CLK,RESET)
begin
if RESET='1' then
ADRi <= "00000000000000000000000000000000";
elsif CLK'event and CLK='1' then
if CycBegin = '1' then
ADRi(23 downto 2) <= DIN(23 downto 2);
elsif INC_ADR = '1' then
ADRi <= ADRi_New;
end if;
end if;
end process;
pADRINC: process(ADRi,INC_ADR)
begin
if INC_ADR ='1' then
ADRi_New <= ADRi + 4;
else
ADRi_New <= ADRi;
end if;
end process;
end RTL;