?? control.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use work.state_pack.all;
entity control is
port(A,B,C,D,E,F,G,CLK : in std_logic;
H,I,J,K,L,M : out std_logic);
end control;
architecture control_arc of control is
signal current_state : state:=QA;
begin
process
begin
wait until CLK'event and CLK ='1';
M<='1';
case current_state is
when QA=>H<='0';
if(A='0')then
current_state<=QA;
else
current_state<=QB;
m<='0';L<='1';K<='1';
when QB=>M<='1';H<='0';
if(C='0')then
current_state<=QB;
else
current_state<=QC;
J<='1';
end if;
when QC=>J<='0';I<='0';H<='1';
if(D='1')then
current_state<=QF;
K<='0';
elsif(C='1')then
current_state<=QC;
J<='1';
elsif(G='1')then
current_state<=QD;
elsif(E='0')then
current_state<=QC;
else
I<='1';
if(F='0')then
current_state<=QE;
elsif(G='1')then
current_state<=QD;
else
current_state<=QC;
end if;
end if;
when QD=>H<='1';
if(E='1')then
current_state<=QE;
elsif(C='1')then
current_state<=QC;
J<='1';
elsif(D='0')then
current_state<=QD;
else
L<='0';
current_state<=QA;
end if;
when QE=>H<='1';
if(C='1')then
current_state<=QC;
J<='1';
elsif(D='0')then
current_state<=QE;
else
K<='0';
current_state<=QF;
end if;
when QF=>H<='0';
if(B='0')then
current_state<=QF;
else
current_state<=QB;
K<='1';M<='0';
end if;
end case;
end process;
end control_arc;
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