library ieee;
use ieee.std_logic_1164.all;

entity kcoun20 is
        port(A  : in std_logic;
             B  : out std_logic);

end kcoun20;

architecture kcoun20_arc of kcoun20 is
       signal counter : std_logic;
begin
    process(A)
    variable counter1 : integer range 0 to 15;
    constant md : integer :=10;
    begin 
          if(A'event and A = '1')then
             if(counter1 = md)then
                 counter1:=0;
                 counter <= not counter;
                 B  <= counter;
              end if;
               counter1:= counter1 + 1;
          end if;
    end process;
end kcoun20_arc;