-- MAX+plus II Compiler Fit File      
-- Version 10.1 06/12/2001            
-- Compiled: 03/24/2008 22:23:36      

-- Copyright (C) 1988-2001 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "direct"
BEGIN

    DEVICE = "EPF10K10LC84-3";

    "A"                            : INPUT_PIN  = 2      ;
    "B"                            : OUTPUT_PIN = 17     ;
    "B~1"                          : LOCATION   = LC2_A10;

END;

INTERNAL_INFO "direct"
BEGIN
	DEVICE = EPF10K10LC84-3;
    OD1P2   : LORAX = "1:FB1|2:FH1R0,PA20R0C9->LC2_A10||";
    LC2_A10 : LORAX = "1:MSW2R0C8,HHL1R0->OH10R0P17|";
	LC2_A10 : LORAX2 = "X, X, X, OD1P2";
END;