------------------------------------------------------------------------
-- Title      2X2 matrix's SVD          --
-- ENTITY     CORDIC_SVD

--!!!Entity ARCTANT and Entity ROTATION should be included!!!                           
------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
--use IEEE.std_logic_signed.all ;
--use IEEE.std_logic_arith.all ;

------------------------------------------------------------------------
-- entity                                                             --
------------------------------------------------------------------------
entity CORDIC_SVD is
    port(
        -- Input/Output Data format = Fixed Point Value
        --     range -1.99994 to 1.99994 2's complement
        -- 15  14 . 13  12  11  10  09  08  07  06  05  04  03  02  01  00
        -- Sign   ^point
        --
        A    : in    std_logic_vector(15 downto 0) ; 
        B    : in    std_logic_vector(15 downto 0) ; 
        C    : in    std_logic_vector(15 downto 0) ; 
        D    : in    std_logic_vector(15 downto 0) ; 
        IN_START0    : in    std_logic ;                     -- convert start
        CLK0         : in    std_logic ;                     -- System Clock
        ENABLE0      : in    std_logic ;                     -- Clock Enable
        XRST0        : in    std_logic ;                     -- Reset
     --!OUT_FINISH   : out   std_logic ;                     -- Convert end
     --!OUT_X        : out   std_logic_vector(15 downto 0) ; -- Calculate X
     --!OUT_Y        : out   std_logic_vector(15 downto 0) ; -- Calculate Y
        DIAG1       : out   std_logic_vector(15 downto 0);   -- Calculate DIAG1
        DIAG2        : out   std_logic_vector(15 downto 0);   -- Calculate DIAG2
        B2           : out   std_logic_vector(15 downto 0);
        C2           : out   std_logic_vector(15 downto 0) 
        ); 
END CORDIC_SVD ; 

------------------------------------------------------------------------
-- architecture                                                       --
------------------------------------------------------------------------

architecture RTL of CORDIC_SVD is

-----------------------------------------------------------
-- COMPONENTS                                            --
-----------------------------------------------------------   
  COMPONENT CORDIC_ARCTANT
    PORT(
        IN_X,IN_Y   : in    std_logic_vector(15 downto 0) ; -- atan(y/X)    -0.15 to 1.0
        IN_START    : in    std_logic ;                     -- convert start
        CLK         : in    std_logic ;                     -- System Clock
        ENABLE      : in    std_logic ;                     -- Clock Enable
        XRST        : in    std_logic ;                     -- Reset
     --!OUT_FINISH  : out   std_logic ;                     -- Convert end
        OUT_Z       : out   std_logic_vector(15 downto 0)   -- Calculate Z
        );
  END COMPONENT;

  COMPONENT CORDIC_ROTATION
    PORT(
        IN_X        : in    std_logic_vector(15 downto 0) ; -- 
        IN_Y        : in    std_logic_vector(15 downto 0) ; -- 
        IN_ANGLE    : in    std_logic_vector(15 downto 0) ; -- 
        IN_START    : in    std_logic ;                     -- convert start
        CLK         : in    std_logic ;                     -- System Clock
        ENABLE      : in    std_logic ;                     -- Clock Enable
        XRST        : in    std_logic ;                     -- Reset
     --!OUT_FINISH  : out   std_logic ;                     -- Convert end
        OUT_X       : out   std_logic_vector(15 downto 0) ; -- Calculate X
        OUT_Y       : out   std_logic_vector(15 downto 0)   -- Calculate Y
        );
  END COMPONENT;
-----------------------------------------------------------
-- Signals                                               --
-----------------------------------------------------------
signal  THETA_RaddL     : std_logic_vector(15 downto 0) ;  
signal  THETA_RsubL     : std_logic_vector(15 downto 0) ;  
signal  D_THETA_R       : std_logic_vector(15 downto 0) ;
signal  D_THETA_L       : std_logic_vector(15 downto 0) ;
signal  THETA_R         : std_logic_vector(15 downto 0) ;
signal  THETA_L         : std_logic_vector(15 downto 0) ;
signal  TEMP1           : std_logic_vector(15 downto 0) ;
signal  TEMP2           : std_logic_vector(15 downto 0) ;
signal  TEMP3           : std_logic_vector(15 downto 0) ;
signal  TEMP4           : std_logic_vector(15 downto 0) ;
signal  A1              : std_logic_vector(15 downto 0) ;
signal  B1              : std_logic_vector(15 downto 0) ;
signal  C1              : std_logic_vector(15 downto 0) ;
signal  D1              : std_logic_vector(15 downto 0) ;

BEGIN

TEMP1 <= D-A;
TEMP2 <= C+B;
TEMP3 <= D+A;
TEMP4 <= C-B;

ARCTANT1 : CORDIC_ARCTANT
    PORT MAP(IN_X => TEMP1, IN_Y => TEMP2, IN_START => IN_START0, CLK => CLK0, ENABLE => ENABLE0, XRST =>XRST0, OUT_Z =>THETA_RaddL);

ARCTANT2 : CORDIC_ARCTANT
    PORT MAP(IN_X => TEMP3, IN_Y => TEMP4, IN_START => IN_START0, CLK => CLK0, ENABLE => ENABLE0, XRST =>XRST0, OUT_Z => THETA_RsubL);

ROTATION_1 : CORDIC_ROTATION
    PORT MAP(IN_X => A, IN_Y => C, IN_ANGLE => THETA_L, IN_START => IN_START0, CLK => CLK0, ENABLE => ENABLE0, XRST =>XRST0, OUT_X => A1, OUT_Y => C1);

ROTATION_2 : CORDIC_ROTATION    
    PORT MAP(IN_X => B, IN_Y => D, IN_ANGLE => THETA_L, IN_START => IN_START0, CLK => CLK0, ENABLE => ENABLE0, XRST =>XRST0, OUT_X => B1, OUT_Y => D1);

ROTATION_3 : CORDIC_ROTATION
    PORT MAP(IN_X => A1, IN_Y => B1, IN_ANGLE => THETA_R, IN_START => IN_START0, CLK => CLK0, ENABLE => ENABLE0, XRST =>XRST0, OUT_X => DIAG1, OUT_Y => B2);

ROTATION_4 : CORDIC_ROTATION
    PORT MAP(IN_X => C1, IN_Y => D1, IN_ANGLE => THETA_R, IN_START => IN_START0, CLK => CLK0, ENABLE => ENABLE0, XRST =>XRST0, OUT_X => DIAG2, OUT_Y => C2);

D_THETA_R <= THETA_RaddL + THETA_RsubL;

D_THETA_L <= THETA_RaddL - THETA_RsubL;

THETA_R <= D_THETA_R(15) & D_THETA_R(15 DOWNTO 1);

THETA_L <= D_THETA_L(15) & D_THETA_L(15 DOWNTO 1);

END RTL;

------------------------------------------------------------------------
-- End of File (!!!!Full Compilation Success!!!!!! )                                                       --
------------------------------------------------------------------------