# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		fir_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:01:25  MAY 17, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 5.0
set_global_assignment -name VHDL_FILE dff89.vhd
set_global_assignment -name VHDL_FILE add888.vhd
set_global_assignment -name VHDL_FILE dff15.vhd
set_global_assignment -name VHDL_FILE mult52.vhd
set_global_assignment -name VHDL_FILE add121313.vhd
set_global_assignment -name VHDL_FILE add121414.vhd
set_global_assignment -name VHDL_FILE add121616.vhd
set_global_assignment -name VHDL_FILE add141616.vhd
set_global_assignment -name VHDL_FILE add889.vhd
set_global_assignment -name VHDL_FILE dff8.vhd
set_global_assignment -name VHDL_FILE mult12.vhd
set_global_assignment -name VHDL_FILE mult13.vhd
set_global_assignment -name VHDL_FILE mult14.vhd
set_global_assignment -name VHDL_FILE mult162.vhd
set_global_assignment -name VHDL_FILE mult18.vhd
set_global_assignment -name VHDL_FILE mult242.vhd
set_global_assignment -name VHDL_FILE mult29.vhd
set_global_assignment -name VHDL_FILE sub131314.vhd
set_global_assignment -name VHDL_FILE sub141616.vhd
set_global_assignment -name BDF_FILE fir.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE fir.vwf

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY fir

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C3T100C6