?? high_zero.vhd
字號:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity high_zero is
port
( a2: in std_logic_vector ( 7 downto 0 );
b2 : out std_logic_vector ( 8 downto 0 )
);
end high_zero;
architecture answer4 of high_zero is
begin
b2 <= '0'&a2;
end answer4;
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