?? jfqs_multiplier.tan.rpt
字號(hào):
Timing Analyzer report for jfqs_multiplier
Fri Jun 20 23:22:10 2008
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clock'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+-----------------+------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-----------------+------------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 3.850 ns ; multiplicand[0] ; c2[0] ; ; clock ; 0 ;
; Worst-case tco ; N/A ; None ; 6.071 ns ; product[1]~reg0 ; product[1] ; clock ; ; 0 ;
; Worst-case th ; N/A ; None ; -1.046 ns ; multiplicand[4] ; c2[4] ; ; clock ; 0 ;
; Clock Setup: 'clock' ; N/A ; None ; 115.27 MHz ( period = 8.675 ns ) ; c2[0] ; product[15]~reg0 ; clock ; clock ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+-----------------+------------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; On ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock ; ; User Pin ; NONE ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock' ;
+-------+------------------------------------------------+-------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 115.27 MHz ( period = 8.675 ns ) ; c2[0] ; product[15]~reg0 ; clock ; clock ; None ; None ; 8.448 ns ;
; N/A ; 115.31 MHz ( period = 8.672 ns ) ; c2[1] ; product[15]~reg0 ; clock ; clock ; None ; None ; 8.445 ns ;
; N/A ; 117.52 MHz ( period = 8.509 ns ) ; c2[0] ; product[14]~reg0 ; clock ; clock ; None ; None ; 8.282 ns ;
; N/A ; 117.54 MHz ( period = 8.508 ns ) ; c2[1] ; product[14]~reg0 ; clock ; clock ; None ; None ; 8.281 ns ;
; N/A ; 118.39 MHz ( period = 8.447 ns ) ; c2[0] ; product[13]~reg0 ; clock ; clock ; None ; None ; 8.220 ns ;
; N/A ; 118.40 MHz ( period = 8.446 ns ) ; c2[1] ; product[13]~reg0 ; clock ; clock ; None ; None ; 8.219 ns ;
; N/A ; 119.26 MHz ( period = 8.385 ns ) ; c2[0] ; product[12]~reg0 ; clock ; clock ; None ; None ; 8.158 ns ;
; N/A ; 119.27 MHz ( period = 8.384 ns ) ; c2[1] ; product[12]~reg0 ; clock ; clock ; None ; None ; 8.157 ns ;
; N/A ; 120.93 MHz ( period = 8.269 ns ) ; c2[0] ; product[11]~reg0 ; clock ; clock ; None ; None ; 8.042 ns ;
; N/A ; 120.93 MHz ( period = 8.269 ns ) ; c2[0] ; product[10]~reg0 ; clock ; clock ; None ; None ; 8.042 ns ;
; N/A ; 120.95 MHz ( period = 8.268 ns ) ; c1[0] ; product[15]~reg0 ; clock ; clock ; None ; None ; 8.041 ns ;
; N/A ; 120.95 MHz ( period = 8.268 ns ) ; c2[1] ; product[11]~reg0 ; clock ; clock ; None ; None ; 8.041 ns ;
; N/A ; 120.95 MHz ( period = 8.268 ns ) ; c2[1] ; product[10]~reg0 ; clock ; clock ; None ; None ; 8.041 ns ;
; N/A ; 121.83 MHz ( period = 8.208 ns ) ; c1[0] ; product[14]~reg0 ; clock ; clock ; None ; None ; 7.981 ns ;
; N/A ; 121.83 MHz ( period = 8.208 ns ) ; c1[0] ; product[13]~reg0 ; clock ; clock ; None ; None ; 7.981 ns ;
; N/A ; 121.83 MHz ( period = 8.208 ns ) ; c1[0] ; product[12]~reg0 ; clock ; clock ; None ; None ; 7.981 ns ;
; N/A ; 121.83 MHz ( period = 8.208 ns ) ; c1[0] ; product[11]~reg0 ; clock ; clock ; None ; None ; 7.981 ns ;
; N/A ; 121.83 MHz ( period = 8.208 ns ) ; c1[0] ; product[10]~reg0 ; clock ; clock ; None ; None ; 7.981 ns ;
; N/A ; 122.79 MHz ( period = 8.144 ns ) ; c1[1] ; product[15]~reg0 ; clock ; clock ; None ; None ; 7.917 ns ;
; N/A ; 123.03 MHz ( period = 8.128 ns ) ; c2[5] ; product[15]~reg0 ; clock ; clock ; None ; None ; 7.901 ns ;
; N/A ; 123.70 MHz ( period = 8.084 ns ) ; c1[1] ; product[14]~reg0 ; clock ; clock ; None ; None ; 7.857 ns ;
; N/A ; 123.70 MHz ( period = 8.084 ns ) ; c1[1] ; product[13]~reg0 ; clock ; clock ; None ; None ; 7.857 ns ;
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