+-------+--------------+------------+------------------+-------------+------------+


+------------------------------------------------------------------------------+
; th                                                                           ;
+---------------+-------------+-----------+-----------------+-------+----------+
; Minimum Slack ; Required th ; Actual th ; From            ; To    ; To Clock ;
+---------------+-------------+-----------+-----------------+-------+----------+
; N/A           ; None        ; -1.046 ns ; multiplicand[4] ; c2[4] ; clock    ;
; N/A           ; None        ; -3.354 ns ; multiplier[6]   ; c1[6] ; clock    ;
; N/A           ; None        ; -3.367 ns ; multiplier[5]   ; c1[5] ; clock    ;
; N/A           ; None        ; -3.471 ns ; multiplicand[5] ; c2[5] ; clock    ;
; N/A           ; None        ; -3.472 ns ; multiplicand[3] ; c2[3] ; clock    ;
; N/A           ; None        ; -3.473 ns ; multiplicand[6] ; c2[6] ; clock    ;
; N/A           ; None        ; -3.510 ns ; multiplicand[2] ; c2[2] ; clock    ;
; N/A           ; None        ; -3.514 ns ; multiplier[0]   ; c1[0] ; clock    ;
; N/A           ; None        ; -3.521 ns ; multiplier[4]   ; c1[4] ; clock    ;
; N/A           ; None        ; -3.603 ns ; multiplier[3]   ; c1[3] ; clock    ;
; N/A           ; None        ; -3.606 ns ; multiplicand[7] ; c2[7] ; clock    ;
; N/A           ; None        ; -3.607 ns ; multiplier[7]   ; c1[7] ; clock    ;
; N/A           ; None        ; -3.615 ns ; multiplicand[1] ; c2[1] ; clock    ;
; N/A           ; None        ; -3.729 ns ; multiplier[1]   ; c1[1] ; clock    ;
; N/A           ; None        ; -3.730 ns ; multiplier[2]   ; c1[2] ; clock    ;
; N/A           ; None        ; -3.809 ns ; multiplicand[0] ; c2[0] ; clock    ;
+---------------+-------------+-----------+-----------------+-------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Jun 20 23:22:10 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off jfqs_multiplier -c jfqs_multiplier --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" has Internal fmax of 115.27 MHz between source register "c2[0]" and destination register "product[15]~reg0" (period= 8.675 ns)
    Info: + Longest register to register delay is 8.448 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y11_N9; Fanout = 8; REG Node = 'c2[0]'
        Info: 2: + IC(1.493 ns) + CELL(0.340 ns) = 1.833 ns; Loc. = LC_X26_Y10_N9; Fanout = 3; COMB Node = 'and_mode:U2|out1[0]~73'
        Info: 3: + IC(1.464 ns) + CELL(0.326 ns) = 3.623 ns; Loc. = LC_X26_Y10_N0; Fanout = 2; COMB Node = 'add1:U13|add~153'
        Info: 4: + IC(0.000 ns) + CELL(0.060 ns) = 3.683 ns; Loc. = LC_X26_Y10_N1; Fanout = 2; COMB Node = 'add1:U13|add~158'
        Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 3.743 ns; Loc. = LC_X26_Y10_N2; Fanout = 2; COMB Node = 'add1:U13|add~163'
        Info: 6: + IC(0.000 ns) + CELL(0.060 ns) = 3.803 ns; Loc. = LC_X26_Y10_N3; Fanout = 2; COMB Node = 'add1:U13|add~168'
        Info: 7: + IC(0.000 ns) + CELL(0.137 ns) = 3.940 ns; Loc. = LC_X26_Y10_N4; Fanout = 4; COMB Node = 'add1:U13|add~173'
        Info: 8: + IC(0.000 ns) + CELL(0.478 ns) = 4.418 ns; Loc. = LC_X26_Y10_N6; Fanout = 3; COMB Node = 'add1:U13|add~181'
        Info: 9: + IC(0.848 ns) + CELL(0.333 ns) = 5.599 ns; Loc. = LC_X25_Y10_N5; Fanout = 2; COMB Node = 'add2:U20|add~240COUT1_268'
        Info: 10: + IC(0.000 ns) + CELL(0.062 ns) = 5.661 ns; Loc. = LC_X25_Y10_N6; Fanout = 2; COMB Node = 'add2:U20|add~245COUT1_269'
        Info: 11: + IC(0.000 ns) + CELL(0.062 ns) = 5.723 ns; Loc. = LC_X25_Y10_N7; Fanout = 2; COMB Node = 'add2:U20|add~250COUT1_270'
        Info: 12: + IC(0.000 ns) + CELL(0.468 ns) = 6.191 ns; Loc. = LC_X25_Y10_N8; Fanout = 2; COMB Node = 'add2:U20|add~253'
        Info: 13: + IC(1.162 ns) + CELL(0.449 ns) = 7.802 ns; Loc. = LC_X24_Y9_N4; Fanout = 1; COMB Node = 'product[14]~157'
        Info: 14: + IC(0.000 ns) + CELL(0.646 ns) = 8.448 ns; Loc. = LC_X24_Y9_N5; Fanout = 1; REG Node = 'product[15]~reg0'
        Info: Total cell delay = 3.481 ns ( 41.21 % )
        Info: Total interconnect delay = 4.967 ns ( 58.79 % )
    Info: - Smallest clock skew is -0.025 ns
        Info: + Shortest clock path from clock "clock" to destination register is 2.237 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clock'
            Info: 2: + IC(0.560 ns) + CELL(0.547 ns) = 2.237 ns; Loc. = LC_X24_Y9_N5; Fanout = 1; REG Node = 'product[15]~reg0'
            Info: Total cell delay = 1.677 ns ( 74.97 % )
            Info: Total interconnect delay = 0.560 ns ( 25.03 % )
        Info: - Longest clock path from clock "clock" to source register is 2.262 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clock'
            Info: 2: + IC(0.585 ns) + CELL(0.547 ns) = 2.262 ns; Loc. = LC_X23_Y11_N9; Fanout = 8; REG Node = 'c2[0]'
            Info: Total cell delay = 1.677 ns ( 74.14 % )
            Info: Total interconnect delay = 0.585 ns ( 25.86 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Micro setup delay of destination is 0.029 ns
Info: tsu for register "c2[0]" (data pin = "multiplicand[0]", clock pin = "clock") is 3.850 ns
    Info: + Longest pin to register delay is 6.083 ns
        Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_97; Fanout = 1; PIN Node = 'multiplicand[0]'
        Info: 2: + IC(4.859 ns) + CELL(0.089 ns) = 6.083 ns; Loc. = LC_X23_Y11_N9; Fanout = 8; REG Node = 'c2[0]'
        Info: Total cell delay = 1.224 ns ( 20.12 % )
        Info: Total interconnect delay = 4.859 ns ( 79.88 % )
    Info: + Micro setup delay of destination is 0.029 ns
    Info: - Shortest clock path from clock "clock" to destination register is 2.262 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clock'
        Info: 2: + IC(0.585 ns) + CELL(0.547 ns) = 2.262 ns; Loc. = LC_X23_Y11_N9; Fanout = 8; REG Node = 'c2[0]'
        Info: Total cell delay = 1.677 ns ( 74.14 % )
        Info: Total interconnect delay = 0.585 ns ( 25.86 % )
Info: tco from clock "clock" to destination pin "product[1]" through register "product[1]~reg0" is 6.071 ns
    Info: + Longest clock path from clock "clock" to source register is 2.262 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clock'
        Info: 2: + IC(0.585 ns) + CELL(0.547 ns) = 2.262 ns; Loc. = LC_X23_Y11_N0; Fanout = 1; REG Node = 'product[1]~reg0'
        Info: Total cell delay = 1.677 ns ( 74.14 % )
        Info: Total interconnect delay = 0.585 ns ( 25.86 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 3.636 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y11_N0; Fanout = 1; REG Node = 'product[1]~reg0'
        Info: 2: + IC(2.014 ns) + CELL(1.622 ns) = 3.636 ns; Loc. = PIN_199; Fanout = 0; PIN Node = 'product[1]'
        Info: Total cell delay = 1.622 ns ( 44.61 % )
        Info: Total interconnect delay = 2.014 ns ( 55.39 % )
Info: th for register "c2[4]" (data pin = "multiplicand[4]", clock pin = "clock") is -1.046 ns
    Info: + Longest clock path from clock "clock" to destination register is 2.262 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clock'
        Info: 2: + IC(0.585 ns) + CELL(0.547 ns) = 2.262 ns; Loc. = LC_X25_Y12_N0; Fanout = 8; REG Node = 'c2[4]'
        Info: Total cell delay = 1.677 ns ( 74.14 % )
        Info: Total interconnect delay = 0.585 ns ( 25.86 % )
    Info: + Micro hold delay of destination is 0.012 ns
    Info: - Shortest pin to register delay is 3.320 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_28; Fanout = 1; PIN Node = 'multiplicand[4]'
        Info: 2: + IC(2.101 ns) + CELL(0.089 ns) = 3.320 ns; Loc. = LC_X25_Y12_N0; Fanout = 8; REG Node = 'c2[4]'
        Info: Total cell delay = 1.219 ns ( 36.72 % )
        Info: Total interconnect delay = 2.101 ns ( 63.28 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Jun 20 23:22:10 2008
    Info: Elapsed time: 00:00:01