?? low_zero.vhd
字號:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity low_zero is
port
( a1 : in std_logic_vector ( 7 downto 0 );
b1 : out std_logic_vector ( 8 downto 0 )
);
end low_zero;
architecture answer3 of low_zero is
begin
b1 <= a1&'0';
end answer3;
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