library IEEE; 
use IEEE.STD_LOGIC_1164.ALL;  
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

entity jfqs_multiplier is
port
    (
       multiplier: in std_logic_vector (7 downto 0);
       multiplicand: in std_logic_vector (7 downto 0);
       clock: in std_logic;
       product: out std_logic_vector ( 15 DOWNTO 0 )
     );
end jfqs_multiplier; 

architecture answer of jfqs_multiplier is

COMPONENT add1
port
    ( 
      addend1,addend2: in std_logic_vector ( 8 downto 0 );
      augend: out std_logic_vector ( 9 downto 0 )

    );
END COMPONENT;

COMPONENT add2
port
    ( --clk: in std_logic;
      adde1,adde2: in std_logic_vector ( 15 downto 0 );
      aug: out std_logic_vector ( 15 downto 0 )
    );
END COMPONENT;

COMPONENT and_mode
port 
       ( 
         and1: in std_logic_vector(7 downto 0);
         and2: in std_logic;
         out1: out std_logic_vector(7 downto 0)
       );
END COMPONENT;

COMPONENT low_zero
port
     ( a1 : in std_logic_vector ( 7 downto 0 );
       b1 : out std_logic_vector ( 8 downto 0 )
     );
END COMPONENT;

COMPONENT high_zero
port
     ( a2: in std_logic_vector ( 7 downto 0 );
       b2 : out std_logic_vector ( 8 downto 0 )
     );
END COMPONENT;

--signal clk_in,temp: std_logic;
signal c1,c2: std_logic_vector ( 7 downto 0 );--multiplier and multiplicand
signal d1,d2,d3,d4,d5,d6,d7,d8: std_logic_vector ( 7 downto 0 ); --and_mode
signal q1,q2,q3,q4,q5,q6,q7,q8: std_logic_vector ( 8 downto 0 ); --low and high zero
signal m1,m2,m3,m4: std_logic_vector ( 9 downto 0 );--the 4 result before the last two addend
signal y1,y2,y: std_logic_vector ( 15 downto 0 );-- the last part

begin
   
process(clock,multiplier,multiplicand)
 begin
 if clock'event and clock='1' then
   c1 <= multiplier;
   c2 <= multiplicand;
 end if;
 end process;
---------------------------------------------------------------------
--and_mode
---------------------------------------------------------------------


 U0: and_mode
        port map(
   
                   and1  => c2,
                   and2  => c1(7),
                   out1  => d1
                 );

 U1: and_mode
        port map(
            
                   and1  => c2,
                   and2  => c1(6),
                   out1  => d2
                 );

 U2: and_mode
        port map(
                 
                   and1  => c2,
                   and2  => c1(5),
                   out1  => d3
                 );

 U3: and_mode
        port map(
                 
                   and1  => c2,
                   and2  => c1(4),
                   out1  => d4
                 );

 U4: and_mode
        port map(
               
                   and1  => c2,
                   and2  => c1(3),
                   out1  => d5
                 );

 U5: and_mode
        port map(
                 
                   and1  => c2,
                   and2  => c1(2),
                   out1  => d6
                 );

 U6: and_mode
        port map(
                 
                   and1  => c2,
                   and2  => c1(1),
                   out1  => d7
                 );

 U7: and_mode
        port map(
               
                   and1  => c2,
                   and2  => c1(0),
                   out1  => d8
                 );
---------------------------------------------------------------------
--the max part,the output is m1 ( 9 downto 0 )
---------------------------------------------------------------------
 U8: low_zero
        port map(
                   a1  => d1,
                   b1  => q1
                 );

 U9: high_zero
        port map(
                   a2  => d2,
                   b2  => q2
                 );

 U10: add1
        port map(
                  addend1  => q1,
                  addend2  => q2,
                  augend   => m1

                 );

---------------------------------------------------------------------
--the second part,the output is m2 ( 9 downto 0 )
---------------------------------------------------------------------
 U11: low_zero
        port map(
                   a1  => d3,
                   b1  => q3
                 );

 U12: high_zero
        port map(
                   a2  => d4,
                   b2  => q4
                 );

 U13: add1
        port map(
                  addend1  => q3,
                  addend2  => q4,
                  augend   => m2

                 );

---------------------------------------------------------------------
--the third part,the output is m3 ( 9 downto 0 )
---------------------------------------------------------------------
 U14: low_zero
        port map(
                   a1  => d5,
                   b1  => q5
                 );

 U15: high_zero
        port map(
                   a2  => d6,
                   b2  => q6
                 );

 U16: add1
        port map(
                  addend1  => q5,
                  addend2  => q6,
                  augend   => m3

                 );

---------------------------------------------------------------------
--the last and also the min part,the output is m4 ( 9 downto 0 )
---------------------------------------------------------------------
 U17: low_zero
        port map(
                   a1  => d7,
                   b1  => q7
                 );

 U18: high_zero
        port map(
                   a2  => d8,
                   b2  => q8
                 );

 U19: add1
        port map(
                  addend1  => q7,
                  addend2  => q8,
                  augend   => m4

                 );

---------------------------------------------------------------------
--extend the above 10 bit to 16 bit and complete the add2 process
---------------------------------------------------------------------
 U20: add2
        port map( 
                  adde1  => m1&"000000",
                  adde2  => "00"&m2&"0000",
                  aug    => y1

                 );

 U21: add2
        port map(
                  adde1  => "0000"&m3&"00",
                  adde2  => "000000"&m4,
                  aug    => y2

                 );

 U22: add2
        port map(
                  adde1  => y1,
                  adde2  => y2,
                  aug    => y

                 );

process(clock)
begin
if clock'event and clock='1' then
product <= y;
end if;
end process;
 end answer;