library IEEE; 
use IEEE.STD_LOGIC_1164.ALL;  
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

entity add2 is
port
    ( --clk:in std_logic;
      adde1,adde2: in std_logic_vector ( 15 downto 0 );
      aug: out std_logic_vector ( 15 downto 0 )
    );
end add2;

architecture answer5 of add2 is
   begin
      process( adde1,adde2)
        begin
               --if clk'event and clk='1' then
               aug <=adde1 + adde2;
               --end if;
     end process;
end answer5;