library IEEE; 
use IEEE.STD_LOGIC_1164.ALL;  
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

entity add1 is
port
    ( 
      addend1,addend2: in std_logic_vector ( 8 downto 0 );
      augend: out std_logic_vector ( 9 downto 0 )
    );
end add1;

architecture answer1 of add1 is
  signal l1,l2: std_logic_vector ( 9 downto 0 );

   begin
      process( addend1,addend2 )

        begin
           l1 <= '0'&addend1;
           l2 <= '0'&addend2;
               augend <=l1 + l2;

     end process;
end answer1;