?? and_mode.vhd
字號:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and_mode is
port
(
and1: in std_logic_vector(7 downto 0);
and2: in std_logic;
out1: out std_logic_vector(7 downto 0)
);
end and_mode;
architecture answer2 of and_mode is
begin
process (and1,and2)
begin
if and2 ='0' then
out1<="00000000";
else
out1<=and1;
end if;
end process;
end answer2;
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