library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tiaoshi is

  port
	(  flag2   : in  std_logic;                     --調時標志
	   sure    : in  std_logic;
         up    : in  std_logic;
       sec1    : out std_logic_vector (3 downto 0); --調時輸出
       sec2    : out std_logic_vector (3 downto 0);
       hour1   : out std_logic_vector (3 downto 0);
       hour2   : out std_logic_vector (3 downto 0)
);
end entity;

architecture arc of tiaoshi is
signal count      :  std_logic_vector (1 downto 0);
begin

process(up,count)
variable data1  :  std_logic_vector (3 downto 0);
 begin
if(count /= "00" or flag2='0') then null;
elsif(up'event and up='1')then
     if(data1="1001")then data1:="0000";
           else
       data1:=data1+1;
     end if;
end if;
 sec1<=data1;
end process;



process(up,count)
variable data2  :  std_logic_vector (3 downto 0);
 begin
if(count /= "01"or flag2='0') then null;
elsif(up'event and up='1')then
     if(data2="1001")then data2:="0000";
          else
            data2:=data2+1;
     end if;
end if;
 sec2<=data2;
end process;

process(up,count)
variable data3  :  std_logic_vector (3 downto 0);
 begin
if(count /= "10"or flag2='0') then null;
elsif(up'event and up='1')then
   if(data3="1001")then data3:="0000";
      else
       data3:=data3+1;
   end if;
end if;
hour1<=data3;
end process;



process(up,count)
variable data4  :  std_logic_vector (3 downto 0);
 begin
if(count /= "11"or flag2='0') then null;
elsif(up'event and up='1')then
   if(data4="1001")then data4:="0000";
      else
       data4:=data4+1;
   end if;
end if;
hour2<=data4;
end process;


process(sure) is
variable count1  :  std_logic_vector (1 downto 0):="00";
begin
if( flag2='0') then null;
 elsif(sure'event and sure='1')then
   if(count1="11")then count1:="00";
   else
        count1:=count1+1;
   end if;

end if;
count<=count1;
end process;

end arc;