library ieee;
use ieee.std_logic_1164.all;
entity diff is

  port
	(  
        cp    : in  std_logic;
        d     : in  std_logic;
	    q     : out std_logic;
        qb    : out std_logic
     );
end entity;
architecture arc of diff is
begin
process(cp) is
begin
if(cp'event and cp='1')then
       q<=d;
      qb<=not d;
end if;
end process;
end arc;