library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity saomiaoxianshi is
--clk 掃描脈沖
--p1,p2,p3,p4,p5,p6,p7 輸入數(shù)據(jù)
-- choice 位選信號
--data  數(shù)碼顯示信號輸出
  port(
		clk		: in	std_logic;
		flag0,flag1,flag2 ,switch  : in	std_logic;
	    p7		: in	std_logic_vector(3 downto 0);
		p6		: in	std_logic_vector(3 downto 0);
		p5		: in	std_logic_vector(3 downto 0);
		p4		: in	std_logic_vector(3 downto 0);
		p3		: in	std_logic_vector(3 downto 0);
		p2		: in	std_logic_vector(3 downto 0);
		p1		: in	std_logic_vector(3 downto 0);
		choice	: out	std_logic_vector(2 downto 0);
		data	: out	std_logic_vector(7 downto 0));
end saomiaoxianshi;


architecture arc of saomiaoxianshi is
	signal count    : std_logic_vector(2 downto 0);
	signal temp     : std_logic_vector(3 downto 0);
	signal datain	: std_logic_vector(6 downto 0);
begin 
--pr1 七進(jìn)制計數(shù)
pr1:process(clk)
begin
if(clk'event and clk='1') then
  if(count="110") then count<="000";
  else count<=count+1;
  end if;
end if;
end process pr1;
--pr2掃描顯示
pr2:process(clk)
begin
if(clk'event and clk='0')then
   choice<=count;
   data(7 downto 1)<=datain;
   
end if;
end process pr2;

ptr3: process(flag0,flag1,flag2,clk,switch)
begin
if(clk'event and clk='0')then

if((flag0='1'or flag1='1') and count="001" and switch='0')then data(0)<='1'; 
elsif(flag0='1'and count="010" and switch='1')then data(0)<='1';
elsif(flag2='1'and count="010" )then data(0)<='1';
else
data(0)<='0';
end if;
end if;
end process ptr3;


--譯碼顯示
temp<=	p1 when count="000" else
		p2 when count="001" else
		p3 when count="010" else
		p4 when count="011" else
		p5 when count="100" else
		p6 when count="101" else
		p7;
with temp select
	datain  <= "0111111" when "0000",
			   "0000110" when "0001",
			   "1011011" when "0010",
			   "1001111" when "0011",
			   "1100110" when "0100",
			   "1101101" when "0101",
			   "1111101" when "0110",
			   "0000111" when "0111",
			   "1111111" when "1000",
			   "1101111" when "1001",
			   "1111001" when  others;
end arc;