Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                  e:\eda\saomiaoxianshiyanzhen.rpt
saomiaoxianshiyanzhen

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       14         clk


Device-Specific Information:                  e:\eda\saomiaoxianshiyanzhen.rpt
saomiaoxianshiyanzhen

** EQUATIONS **

clk      : INPUT;
flag0    : INPUT;
flag1    : INPUT;
flag2    : INPUT;
p0       : INPUT;
p1       : INPUT;
p2       : INPUT;
p3       : INPUT;
switch   : INPUT;

-- Node name is 'seg0' 
-- Equation name is 'seg0', type is output 
seg0     =  _LC8_A10;

-- Node name is 'seg1' 
-- Equation name is 'seg1', type is output 
seg1     =  _LC2_B2;

-- Node name is 'seg2' 
-- Equation name is 'seg2', type is output 
seg2     =  _LC4_B2;

-- Node name is 'seg3' 
-- Equation name is 'seg3', type is output 
seg3     =  _LC6_B2;

-- Node name is 'seg4' 
-- Equation name is 'seg4', type is output 
seg4     =  _LC3_B2;

-- Node name is 'seg5' 
-- Equation name is 'seg5', type is output 
seg5     =  _LC1_B2;

-- Node name is 'seg6' 
-- Equation name is 'seg6', type is output 
seg6     =  _LC7_B2;

-- Node name is 'seg7' 
-- Equation name is 'seg7', type is output 
seg7     =  _LC8_B2;

-- Node name is 'sn0' 
-- Equation name is 'sn0', type is output 
sn0      =  _LC1_A10;

-- Node name is 'sn1' 
-- Equation name is 'sn1', type is output 
sn1      =  _LC2_A4;

-- Node name is 'sn2' 
-- Equation name is 'sn2', type is output 
sn2      =  _LC7_A7;

-- Node name is '|SAOMIAOXIANSHI:2|:58' = '|SAOMIAOXIANSHI:2|count0' 
-- Equation name is '_LC4_A10', type is buried 
_LC4_A10 = DFFE( _EQ001, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 = !_LC3_A10 & !_LC4_A10
         # !_LC2_A10 & !_LC4_A10;

-- Node name is '|SAOMIAOXIANSHI:2|:57' = '|SAOMIAOXIANSHI:2|count1' 
-- Equation name is '_LC6_A10', type is buried 
_LC6_A10 = DFFE( _EQ002, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 = !_LC3_A10 & !_LC4_A10 &  _LC6_A10
         # !_LC2_A10 & !_LC4_A10 &  _LC6_A10
         # !_LC3_A10 &  _LC4_A10 & !_LC6_A10
         # !_LC2_A10 &  _LC4_A10 & !_LC6_A10;

-- Node name is '|SAOMIAOXIANSHI:2|:56' = '|SAOMIAOXIANSHI:2|count2' 
-- Equation name is '_LC3_A10', type is buried 
_LC3_A10 = DFFE( _EQ003, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 = !_LC3_A10 &  _LC4_A10 &  _LC6_A10
         # !_LC2_A10 &  _LC3_A10 & !_LC6_A10
         # !_LC2_A10 &  _LC3_A10 & !_LC4_A10;

-- Node name is '|SAOMIAOXIANSHI:2|:34' 
-- Equation name is '_LC7_A7', type is buried 
_LC7_A7  = DFFE( _LC3_A10, GLOBAL(!clk),  VCC,  VCC,  VCC);

-- Node name is '|SAOMIAOXIANSHI:2|:36' 
-- Equation name is '_LC2_A4', type is buried 
_LC2_A4  = DFFE( _LC6_A10, GLOBAL(!clk),  VCC,  VCC,  VCC);

-- Node name is '|SAOMIAOXIANSHI:2|:38' 
-- Equation name is '_LC1_A10', type is buried 
_LC1_A10 = DFFE( _LC4_A10, GLOBAL(!clk),  VCC,  VCC,  VCC);

-- Node name is '|SAOMIAOXIANSHI:2|:40' 
-- Equation name is '_LC8_B2', type is buried 
_LC8_B2  = DFFE( _EQ004, GLOBAL(!clk),  VCC,  VCC,  VCC);
  _EQ004 =  p3
         # !p1 &  p2
         # !p0 &  p2
         # !p0 &  p1
         #  p1 & !p2;

-- Node name is '|SAOMIAOXIANSHI:2|:42' 
-- Equation name is '_LC7_B2', type is buried 
_LC7_B2  = DFFE( _EQ005, GLOBAL(!clk),  VCC,  VCC,  VCC);
  _EQ005 =  p3
         # !p0 &  p2
         # !p1 &  p2
         # !p0 & !p1;

-- Node name is '|SAOMIAOXIANSHI:2|:44' 
-- Equation name is '_LC1_B2', type is buried 
_LC1_B2  = DFFE( _EQ006, GLOBAL(!clk),  VCC,  VCC,  VCC);
  _EQ006 =  p2 &  p3
         #  p1 &  p3
         # !p0 & !p2
         # !p0 &  p1
         # !p0 &  p3;

-- Node name is '|SAOMIAOXIANSHI:2|:46' 
-- Equation name is '_LC3_B2', type is buried 
_LC3_B2  = DFFE( _EQ007, GLOBAL(!clk),  VCC,  VCC,  VCC);
  _EQ007 =  p3
         # !p0 &  p1
         #  p1 & !p2
         # !p0 & !p2
         #  p0 & !p1 &  p2;

-- Node name is '|SAOMIAOXIANSHI:2|:48' 
-- Equation name is '_LC6_B2', type is buried 
_LC6_B2  = DFFE( _EQ008, GLOBAL(!clk),  VCC,  VCC,  VCC);
  _EQ008 =  p0 & !p3
         # !p1 & !p3
         #  p2 & !p3
         # !p1 & !p2;

-- Node name is '|SAOMIAOXIANSHI:2|:50' 
-- Equation name is '_LC4_B2', type is buried 
_LC4_B2  = DFFE( _EQ009, GLOBAL(!clk),  VCC,  VCC,  VCC);
  _EQ009 =  p0 &  p1 & !p3
         # !p1 & !p2
         # !p2 & !p3
         # !p0 & !p1 & !p3;

-- Node name is '|SAOMIAOXIANSHI:2|:52' 
-- Equation name is '_LC2_B2', type is buried 
_LC2_B2  = DFFE( _EQ010, GLOBAL(!clk),  VCC,  VCC,  VCC);
  _EQ010 =  p3
         #  p1
         #  p0 &  p2
         # !p0 & !p2;

-- Node name is '|SAOMIAOXIANSHI:2|:54' 
-- Equation name is '_LC8_A10', type is buried 
_LC8_A10 = DFFE( _EQ011, GLOBAL(!clk),  VCC,  VCC,  VCC);
  _EQ011 = !_LC3_A10 &  _LC4_A10 &  _LC5_A10
         # !_LC3_A10 &  _LC7_A10;

-- Node name is '|SAOMIAOXIANSHI:2|~409~1' 
-- Equation name is '_LC5_A10', type is buried 
-- synthesized logic cell 
_LC5_A10 = LCELL( _EQ012);
  _EQ012 =  flag1 & !_LC6_A10 & !switch
         #  flag0 & !_LC6_A10 & !switch;

-- Node name is '|SAOMIAOXIANSHI:2|~650~1' 
-- Equation name is '_LC7_A10', type is buried 
-- synthesized logic cell 
_LC7_A10 = LCELL( _EQ013);
  _EQ013 =  flag2 &  _LC2_A10
         #  flag0 &  _LC2_A10 &  switch;

-- Node name is '|SAOMIAOXIANSHI:2|~710~1' 
-- Equation name is '_LC2_A10', type is buried 
-- synthesized logic cell 
!_LC2_A10 = _LC2_A10~NOT;
_LC2_A10~NOT = LCELL( _EQ014);
  _EQ014 = !_LC6_A10
         #  _LC4_A10;



Project Information                           e:\eda\saomiaoxianshiyanzhen.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 10,400K