?? displayswitch.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity displayswitch is
port
( switch : in std_logic;
up : in std_logic_vector(3 downto 0);
price1 : in std_logic_vector(3 downto 0);
price2 : in std_logic_vector(3 downto 0);
price3 : in std_logic_vector(3 downto 0)
sec1 : in std_logic_vector(3 downto 0);
sec2 : in std_logic_vector(3 downto 0);
hour1 : in std_logic_vector(3 downto 0);
hour2 : in std_logic_vector(3 downto 0);
p1 : in std_logic_vector(3 downto 0);
p2 : in std_logic_vector(3 downto 0);
p3 : in std_logic_vector(3 downto 0);
km1 : in std_logic_vector(3 downto 0);
km2 : in std_logic_vector(3 downto 0);
wait1 : in std_logic_vector(3 downto 0);
wait1 : in std_logic_vector(3 downto 0);
p1 : out std_logic_vector(3 downto 0);
p2 : out std_logic_vector(3 downto 0);
p3 : out std_logic_vector(3 downto 0);
p4 : out std_logic_vector(3 downto 0);
p5 : out std_logic_vector(3 downto 0);
p6 : out std_logic_vector(3 downto 0);
p7 : out std_logic_vector(3 downto 0)
);
end entity;
architecture arc of displayswitch is
data1 : out std_logic_vector(3 downto 0);
data2 : out std_logic_vector(3 downto 0);
data3 : out std_logic_vector(3 downto 0);
data4 : out std_logic_vector(3 downto 0);
data5 : out std_logic_vector(3 downto 0);
data6 : out std_logic_vector(3 downto 0);
data7 : out std_logic_vector(3 downto 0)
begin
process( ) is
begin
if(up'event and up='1')then
flag<='0';
clk0<=not clk0;
end if;
end process;
process(down) is
begin
if(down'event and down='1')then
flag<='1';
clk0<=not clk0;
end if;
end process;
clk<=clk0;
end arc;
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