?? shezhi.vhd
字號(hào):
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shezhi is
port
( mode : in std_logic;
sure : in std_logic;
up : in std_logic;
wait_en : out std_logic;
price1 : out std_logic_vector (3 downto 0);
price2 : out std_logic_vector (3 downto 0);
price3 : out std_logic_vector (3 downto 0);
time1 : out std_logic_vector (3 downto 0);
time2 : out std_logic_vector (3 downto 0);
time3 : out std_logic_vector (3 downto 0);
time4 : out std_logic_vector (3 downto 0);
display : out std_logic_vector (3 downto 0)
);
end entity;
architecture arc of shezhi is
signal data : std_logic_vector (3 downto 0);
signal switch : std_logic_vector (2 downto 0):="000";
begin
p1:process(mode) is
begin
if(mode'event and mode='1')then
switch<=switch+1;
if(switch="111")then
switch<="000";
end if;
end if;
end process;
p2:process(up) is
begin
if(up'event and up='1')then
data<=data+1;
end if;
if data(3)='1' and (not(data(2 downto 1)="00")) then
data<=data+"0110";
end if;
end process;
p3:process(sure) is
begin
if(sure'event and sure='1')then
case switch is
when "000" =>wait_en<=up;
when "001" => price1<=data;
when "010" => price2<=data;
when "011" => price3<=data;
when "100" => time1<=data;
when "101" => time2<=data;
when "110" => time3<=data;
when "111" => time4<=data;
when others=> time1<=data;
end case;
end if;
end process;
display<=data;
end arc;
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