?? count60.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count60 is
--clk 計數(shù)脈沖
--count 計數(shù)輸出
--co 進(jìn)位信號
port
(
clk : in std_logic;
flag2 : in std_logic;
sec1 : in std_logic_vector (3 downto 0);
sec2 : in std_logic_vector (3 downto 0);
time1 : out std_logic_vector(3 downto 0);
time2 : out std_logic_vector(3 downto 0);
co : out std_logic
);
end entity;
architecture rtl of count60 is
begin
process (clk,flag2,sec1,sec2)
variable count :std_logic_vector(7 downto 0);
begin
if(flag2='1') then
count:=sec2 & sec1;
elsif(clk'event and clk='1') then
if (flag2='0') then
if( count="01011001")then
count:="00000000";
co<='1';
else count:=count+1;
co<='0';
end if;
if count(3)='1' and (not(count(2 downto 1)="00")) then
count:=count+"0110";
end if;
end if;
end if;
time1<=count(3 downto 0);
time2<=count(7 downto 4);
end process;
end rtl;
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