?? c8051f020.lst
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C51 COMPILER V6.12 C8051F020 09/03/2007 16:53:05 PAGE 1
C51 COMPILER V6.12, COMPILATION OF MODULE C8051F020
OBJECT MODULE PLACED IN c8051F020.OBJ
COMPILER INVOKED BY: D:\Program Files\keil\C51\BIN\C51.EXE c8051F020.h DB OE
stmt level source
1 /*---------------------------------------------------------------------------
2 ;
3 ;
4 ;
5 ;
6 ; FILE NAME : C8051F020.H
7 ; TARGET MCUs : C8051F020, 'F021, 'F022, 'F023
8 ; DESCRIPTION : Register/bit definitions for the C8051F02x product family.
9 ;
10 ; REVISION 1.1
11 ;
12 ;---------------------------------------------------------------------------*/
13 /* define to prevent recursive inclusion */
14 #ifndef __C8051F020_H
15 #define __C8051F020_H
16
17 /* BYTE Registers */
18 sfr P0 = 0x80; /* PORT 0 */
19 sfr SP = 0x81; /* STACK POINTER */
20 sfr DPL = 0x82; /* DATA POINTER - LOW BYTE */
21 sfr DPH = 0x83; /* DATA POINTER - HIGH BYTE */
22 sfr P4 = 0x84; /* PORT 4 */
23 sfr P5 = 0x85; /* PORT 5 */
24 sfr P6 = 0x86; /* PORT 6 */
25 sfr PCON = 0x87; /* POWER CONTROL */
26 sfr TCON = 0x88; /* TIMER CONTROL */
27 sfr TMOD = 0x89; /* TIMER MODE */
28 sfr TL0 = 0x8A; /* TIMER 0 - LOW BYTE */
29 sfr TL1 = 0x8B; /* TIMER 1 - LOW BYTE */
30 sfr TH0 = 0x8C; /* TIMER 0 - HIGH BYTE */
31 sfr TH1 = 0x8D; /* TIMER 1 - HIGH BYTE */
32 sfr CKCON = 0x8E; /* CLOCK CONTROL */
33 sfr PSCTL = 0x8F; /* PROGRAM STORE R/W CONTROL */
34 sfr P1 = 0x90; /* PORT 1 */
35 sfr TMR3CN = 0x91; /* TIMER 3 CONTROL */
36 sfr TMR3RLL = 0x92; /* TIMER 3 RELOAD REGISTER - LOW BYTE */
37 sfr TMR3RLH = 0x93; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */
38 sfr TMR3L = 0x94; /* TIMER 3 - LOW BYTE */
39 sfr TMR3H = 0x95; /* TIMER 3 - HIGH BYTE */
40 sfr P7 = 0x96; /* PORT 7 */
41 sfr SCON0 = 0x98; /* SERIAL PORT 0 CONTROL */
42 sfr SBUF0 = 0x99; /* SERIAL PORT 0 BUFFER */
43 sfr SPI0CFG = 0x9A; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */
44 sfr SPI0DAT = 0x9B; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
45 sfr ADC1 = 0x9C; /* ADC 1 DATA */
46 sfr SPI0CKR = 0x9D; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */
47 sfr CPT0CN = 0x9E; /* COMPARATOR 0 CONTROL */
48 sfr CPT1CN = 0x9F; /* COMPARATOR 1 CONTROL */
49 sfr P2 = 0xA0; /* PORT 2 */
50 sfr EMI0TC = 0xA1; /* EMIF TIMING CONTROL */
51 sfr EMI0CF = 0xA3; /* EXTERNAL MEMORY INTERFACE (EMIF) CONFIGURATION */
52 sfr P0MDOUT = 0xA4; /* PORT 0 OUTPUT MODE CONFIGURATION */
53 sfr P1MDOUT = 0xA5; /* PORT 1 OUTPUT MODE CONFIGURATION */
54 sfr P2MDOUT = 0xA6; /* PORT 2 OUTPUT MODE CONFIGURATION */
55 sfr P3MDOUT = 0xA7; /* PORT 3 OUTPUT MODE CONFIGURATION */
C51 COMPILER V6.12 C8051F020 09/03/2007 16:53:05 PAGE 2
56 sfr IE = 0xA8; /* INTERRUPT ENABLE */
57 sfr SADDR0 = 0xA9; /* SERIAL PORT 0 SLAVE ADDRESS */
58 sfr ADC1CN = 0xAA; /* ADC 1 CONTROL */
59 sfr ADC1CF = 0xAB; /* ADC 1 ANALOG MUX CONFIGURATION */
60 sfr AMX1SL = 0xAC; /* ADC 1 ANALOG MUX CHANNEL SELECT */
61 sfr P3IF = 0xAD; /* PORT 3 EXTERNAL INTERRUPT FLAGS */
62 sfr SADEN1 = 0xAE; /* SERIAL PORT 1 SLAVE ADDRESS MASK */
63 sfr EMI0CN = 0xAF; /* EXTERNAL MEMORY INTERFACE CONTROL */
64 sfr P3 = 0xB0; /* PORT 3 */
65 sfr OSCXCN = 0xB1; /* EXTERNAL OSCILLATOR CONTROL */
66 sfr OSCICN = 0xB2; /* INTERNAL OSCILLATOR CONTROL */
67 sfr P74OUT = 0xB5; /* PORTS 4 - 7 OUTPUT MODE */
68 sfr FLSCL = 0xB6; /* FLASH MEMORY TIMING PRESCALER */
69 sfr FLACL = 0xB7; /* FLASH ACESS LIMIT */
70 sfr IP = 0xB8; /* INTERRUPT PRIORITY */
71 sfr SADEN0 = 0xB9; /* SERIAL PORT 0 SLAVE ADDRESS MASK */
72 sfr AMX0CF = 0xBA; /* ADC 0 MUX CONFIGURATION */
73 sfr AMX0SL = 0xBB; /* ADC 0 MUX CHANNEL SELECTION */
74 sfr ADC0CF = 0xBC; /* ADC 0 CONFIGURATION */
75 sfr P1MDIN = 0xBD; /* PORT 1 INPUT MODE */
76 sfr ADC0L = 0xBE; /* ADC 0 DATA - LOW BYTE */
77 sfr ADC0H = 0xBF; /* ADC 0 DATA - HIGH BYTE */
78 sfr SMB0CN = 0xC0; /* SMBUS 0 CONTROL */
79 sfr SMB0STA = 0xC1; /* SMBUS 0 STATUS */
80 sfr SMB0DAT = 0xC2; /* SMBUS 0 DATA */
81 sfr SMB0ADR = 0xC3; /* SMBUS 0 SLAVE ADDRESS */
82 sfr ADC0GTL = 0xC4; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
83 sfr ADC0GTH = 0xC5; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
84 sfr ADC0LTL = 0xC6; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
85 sfr ADC0LTH = 0xC7; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
86 sfr T2CON = 0xC8; /* TIMER 2 CONTROL */
87 sfr T4CON = 0xC9; /* TIMER 4 CONTROL */
88 sfr RCAP2L = 0xCA; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
89 sfr RCAP2H = 0xCB; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
90 sfr TL2 = 0xCC; /* TIMER 2 - LOW BYTE */
91 sfr TH2 = 0xCD; /* TIMER 2 - HIGH BYTE */
92 sfr SMB0CR = 0xCF; /* SMBUS 0 CLOCK RATE */
93 sfr PSW = 0xD0; /* PROGRAM STATUS WORD */
94 sfr REF0CN = 0xD1; /* VOLTAGE REFERENCE 0 CONTROL */
95 sfr DAC0L = 0xD2; /* DAC 0 REGISTER - LOW BYTE */
96 sfr DAC0H = 0xD3; /* DAC 0 REGISTER - HIGH BYTE */
97 sfr DAC0CN = 0xD4; /* DAC 0 CONTROL */
98 sfr DAC1L = 0xD5; /* DAC 1 REGISTER - LOW BYTE */
99 sfr DAC1H = 0xD6; /* DAC 1 REGISTER - HIGH BYTE */
100 sfr DAC1CN = 0xD7; /* DAC 1 CONTROL */
101 sfr PCA0CN = 0xD8; /* PCA 0 COUNTER CONTROL */
102 sfr PCA0MD = 0xD9; /* PCA 0 COUNTER MODE */
103 sfr PCA0CPM0 = 0xDA; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */
104 sfr PCA0CPM1 = 0xDB; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */
105 sfr PCA0CPM2 = 0xDC; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */
106 sfr PCA0CPM3 = 0xDD; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */
107 sfr PCA0CPM4 = 0xDE; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */
108 sfr ACC = 0xE0; /* ACCUMULATOR */
109 sfr XBR0 = 0xE1; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */
110 sfr XBR1 = 0xE2; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */
111 sfr XBR2 = 0xE3; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */
112 sfr RCAP4L = 0xE4; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
113 sfr RCAP4H = 0xE5; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
114 sfr EIE1 = 0xE6; /* EXTERNAL INTERRUPT ENABLE 1 */
115 sfr EIE2 = 0xE7; /* EXTERNAL INTERRUPT ENABLE 2 */
116 sfr ADC0CN = 0xE8; /* ADC 0 CONTROL */
117 sfr PCA0L = 0xE9; /* PCA 0 TIMER - LOW BYTE */
C51 COMPILER V6.12 C8051F020 09/03/2007 16:53:05 PAGE 3
118 sfr PCA0CPL0 = 0xEA; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
119 sfr PCA0CPL1 = 0xEB; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
120 sfr PCA0CPL2 = 0xEC; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
121 sfr PCA0CPL3 = 0xED; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
122 sfr PCA0CPL4 = 0xEE; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
123 sfr RSTSRC = 0xEF; /* RESET SOURCE */
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