?? c8051f020.lst
字號:
124 sfr B = 0xF0; /* B REGISTER */
125 sfr SCON1 = 0xF1; /* SERIAL PORT 1 CONTROL */
126 sfr SBUF1 = 0xF2; /* SERAIL PORT 1 DATA */
127 sfr SADDR1 = 0xF3; /* SERAIL PORT 1 */
128 sfr TL4 = 0xF4; /* TIMER 4 DATA - LOW BYTE */
129 sfr TH4 = 0xF5; /* TIMER 4 DATA - HIGH BYTE */
130 sfr EIP1 = 0xF6; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
131 sfr EIP2 = 0xF7; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
132 sfr SPI0CN = 0xF8; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */
133 sfr PCA0H = 0xF9; /* PCA 0 TIMER - HIGH BYTE */
134 sfr PCA0CPH0 = 0xFA; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
135 sfr PCA0CPH1 = 0xFB; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
136 sfr PCA0CPH2 = 0xFC; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
137 sfr PCA0CPH3 = 0xFD; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
138 sfr PCA0CPH4 = 0xFE; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
139 sfr WDTCN = 0xFF; /* WATCHDOG TIMER CONTROL */
140
141
142 /* BIT Registers */
143
144 /* TCON 0x88 */
145 sbit TF1 = TCON ^ 7; /* TIMER 1 OVERFLOW FLAG */
146 sbit TR1 = TCON ^ 6; /* TIMER 1 ON/OFF CONTROL */
147 sbit TF0 = TCON ^ 5; /* TIMER 0 OVERFLOW FLAG */
148 sbit TR0 = TCON ^ 4; /* TIMER 0 ON/OFF CONTROL */
149 sbit IE1 = TCON ^ 3; /* EXT. INTERRUPT 1 EDGE FLAG */
150 sbit IT1 = TCON ^ 2; /* EXT. INTERRUPT 1 TYPE */
151 sbit IE0 = TCON ^ 1; /* EXT. INTERRUPT 0 EDGE FLAG */
152 sbit IT0 = TCON ^ 0; /* EXT. INTERRUPT 0 TYPE */
153
154 /* SCON0 0x98 */
155 sbit SM00 = SCON0 ^ 7; /* SERIAL MODE CONTROL BIT 0 */
156 sbit SM10 = SCON0 ^ 6; /* SERIAL MODE CONTROL BIT 1 */
157 sbit SM20 = SCON0 ^ 5; /* MULTIPROCESSOR COMMUNICATION ENABLE */
158 sbit REN0 = SCON0 ^ 4; /* RECEIVE ENABLE */
159 sbit TB80 = SCON0 ^ 3; /* TRANSMIT BIT 8 */
160 sbit RB80 = SCON0 ^ 2; /* RECEIVE BIT 8 */
161 sbit TI0 = SCON0 ^ 1; /* TRANSMIT INTERRUPT FLAG */
162 sbit RI0 = SCON0 ^ 0; /* RECEIVE INTERRUPT FLAG */
163
164 /* IE 0xA8 */
165 sbit EA = IE ^ 7; /* GLOBAL INTERRUPT ENABLE */
166 sbit ET2 = IE ^ 5; /* TIMER 2 INTERRUPT ENABLE */
167 sbit ES0 = IE ^ 4; /* UART0 INTERRUPT ENABLE */
168 sbit ET1 = IE ^ 3; /* TIMER 1 INTERRUPT ENABLE */
169 sbit EX1 = IE ^ 2; /* EXTERNAL INTERRUPT 1 ENABLE */
170 sbit ET0 = IE ^ 1; /* TIMER 0 INTERRUPT ENABLE */
171 sbit EX0 = IE ^ 0; /* EXTERNAL INTERRUPT 0 ENABLE */
172
173 /* IP 0xB8 */
174 sbit PT2 = IP ^ 5; /* TIMER 2 PRIORITY */
175 sbit PS = IP ^ 4; /* SERIAL PORT PRIORITY */
176 sbit PT1 = IP ^ 3; /* TIMER 1 PRIORITY */
177 sbit PX1 = IP ^ 2; /* EXTERNAL INTERRUPT 1 PRIORITY */
178 sbit PT0 = IP ^ 1; /* TIMER 0 PRIORITY */
179 sbit PX0 = IP ^ 0; /* EXTERNAL INTERRUPT 0 PRIORITY */
C51 COMPILER V6.12 C8051F020 09/03/2007 16:53:05 PAGE 4
180
181 /* SMB0CN 0xC0 */
182 sbit BUSY = SMB0CN ^ 7; /* SMBUS 0 BUSY */
183 sbit ENSMB = SMB0CN ^ 6; /* SMBUS 0 ENABLE */
184 sbit STA = SMB0CN ^ 5; /* SMBUS 0 START FLAG */
185 sbit STO = SMB0CN ^ 4; /* SMBUS 0 STOP FLAG */
186 sbit SI = SMB0CN ^ 3; /* SMBUS 0 INTERRUPT PENDING FLAG */
187 sbit AA = SMB0CN ^ 2; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
188 sbit SMBFTE = SMB0CN ^ 1; /* SMBUS 0 FREE TIMER ENABLE */
189 sbit SMBTOE = SMB0CN ^ 0; /* SMBUS 0 TIMEOUT ENABLE */
190
191 /* T2CON 0xC8 */
192 sbit TF2 = T2CON ^ 7; /* TIMER 2 OVERFLOW FLAG */
193 sbit EXF2 = T2CON ^ 6; /* EXTERNAL FLAG */
194 sbit RCLK0 = T2CON ^ 5; /* UART0 RX CLOCK SOURCE */
195 sbit TCLK0 = T2CON ^ 4; /* UART0 TX CLOCK SOURCE */
196 sbit EXEN2 = T2CON ^ 3; /* TIMER 2 EXTERNAL ENABLE FLAG */
197 sbit TR2 = T2CON ^ 2; /* TIMER 2 ON/OFF CONTROL */
198 sbit CT2 = T2CON ^ 1; /* TIMER OR COUNTER SELECT */
199 sbit CPRL2 = T2CON ^ 0; /* CAPTURE OR RELOAD SELECT */
200
201 /* PSW */
202 sbit CY = PSW ^ 7; /* CARRY FLAG */
203 sbit AC = PSW ^ 6; /* AUXILIARY CARRY FLAG */
204 sbit F0 = PSW ^ 5; /* USER FLAG 0 */
205 sbit RS1 = PSW ^ 4; /* REGISTER BANK SELECT 1 */
206 sbit RS0 = PSW ^ 3; /* REGISTER BANK SELECT 0 */
207 sbit OV = PSW ^ 2; /* OVERFLOW FLAG */
208 sbit F1 = PSW ^ 1; /* USER FLAG 1 */
209 sbit P = PSW ^ 0; /* ACCUMULATOR PARITY FLAG */
210
211 /* PCA0CN D8H */
212 sbit CF = PCA0CN ^ 7; /* PCA 0 COUNTER OVERFLOW FLAG */
213 sbit CR = PCA0CN ^ 6; /* PCA 0 COUNTER RUN CONTROL BIT */
214 sbit CCF4 = PCA0CN ^ 4; /* PCA 0 MODULE 4 INTERRUPT FLAG */
215 sbit CCF3 = PCA0CN ^ 3; /* PCA 0 MODULE 3 INTERRUPT FLAG */
216 sbit CCF2 = PCA0CN ^ 2; /* PCA 0 MODULE 2 INTERRUPT FLAG */
217 sbit CCF1 = PCA0CN ^ 1; /* PCA 0 MODULE 1 INTERRUPT FLAG */
218 sbit CCF0 = PCA0CN ^ 0; /* PCA 0 MODULE 0 INTERRUPT FLAG */
219
220 /* ADC0CN E8H */
221 sbit AD0EN = ADC0CN ^ 7; /* ADC 0 ENABLE */
222 sbit AD0TM = ADC0CN ^ 6; /* ADC 0 TRACK MODE */
223 sbit AD0INT = ADC0CN ^ 5; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
224 sbit AD0BUSY = ADC0CN ^ 4; /* ADC 0 BUSY FLAG */
225 sbit AD0CM1 = ADC0CN ^ 3; /* ADC 0 START OF CONVERSION MODE BIT 1 */
226 sbit AD0CM0 = ADC0CN ^ 2; /* ADC 0 START OF CONVERSION MODE BIT 0 */
227 sbit AD0WINT = ADC0CN ^ 1; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
228 sbit AD0LJST = ADC0CN ^ 0; /* ADC 0 RIGHT JUSTIFY DATA BIT */
229
230 /* SPI0CN F8H */
231 sbit SPIF = SPI0CN ^ 7; /* SPI 0 INTERRUPT FLAG */
232 sbit WCOL = SPI0CN ^ 6; /* SPI 0 WRITE COLLISION FLAG */
233 sbit MODF = SPI0CN ^ 5; /* SPI 0 MODE FAULT FLAG */
234 sbit RXOVRN = SPI0CN ^ 4; /* SPI 0 RX OVERRUN FLAG */
235 sbit TXBSY = SPI0CN ^ 3; /* SPI 0 TX BUSY FLAG */
236 sbit SLVSEL = SPI0CN ^ 2; /* SPI 0 SLAVE SELECT */
237 sbit MSTEN = SPI0CN ^ 1; /* SPI 0 MASTER ENABLE */
238 sbit SPIEN = SPI0CN ^ 0; /* SPI 0 SPI ENABLE */
239
240 #endif
C51 COMPILER V6.12 C8051F020 09/03/2007 16:53:05 PAGE 5
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = ---- ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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