module mealy
title 'Mealy machine description of a Sequence detector
       Data I/O Corp.  by Jeffrey Davis '

        mealy device 'f167';

"Inputs
        clk   pin 1;
        PR    pin 16;
        X     pin 8;

"Output
        Z        pin  15     istype 'buffer,reg_RS';
        Q1, Q0   node 31,32  istype 'reg_RS';

"State Register assignment
        sreg    = [Q1,Q0];
        A       = [ 0, 0];"use one bit changes for better optimization
        B       = [ 0, 1];
        C       = [ 1, 1];

Equations
        sreg.pr  = PR;
        sreg.clk = clk;
        Z.clk    = clk;

state_diagram sreg

state A: 
         if X then B    with Z.r = 1 ; endwith ;
         else A         with Z.r = 1 ; endwith ;

state B: 
         if X then C 
         else A ;

state C: 
         Z.s = X ;
         if X then C
         else A         with Z.r = 1 ; endwith ;

test_vectors
        ([clk,PR, X] -> [ sreg ,  Z  ])
         [.c.,1 , 0] -> [   C  , .x. ];
         [.c.,0 , 0] -> [   A  ,  0  ];
         [.c.,0 , 1] -> [   B  ,  0  ];
         [.c.,0 , 1] -> [   C  ,  0  ];
         [.c.,0 , 1] -> [   C  ,  1  ];
         [.c.,0 , 0] -> [   A  ,  0  ];
         [.c.,0 , 1] -> [   B  ,  0  ];
         [.c.,0 , 1] -> [   C  ,  0  ];
         [.c.,0 , 0] -> [   A  ,  0  ];
         [.c.,0 , 1] -> [   B  ,  0  ];
         [.c.,0 , 0] -> [   A  ,  0  ];
         [.c.,0 , 1] -> [   B  ,  0  ];
         [.c.,0 , 1] -> [   C  ,  0  ];
         [.c.,0 , 1] -> [   C  ,  1  ];
end