module MuxAdd 
title '5-bit ripple adder with input multiplex
Michael Holley   Data I/O Corp.  26 Mar 1990'

        muxadd  device  'P22V10';

        AddClk,Clr,Add10,Sub10,is_Ace   pin  1, 9, 8, 7,14;
        V4,V3,V2,V1,V0                  pin  6, 5, 4, 3, 2;
        S4,S3,S2,S1,S0                  pin 15,16,17,18,19;
        C4,C3,C2,C1                     pin 20,21,22,23;   

        X,C,L,H   = .X., .C., 0, 1;

        Card      = [V4,V3,V2,V1,V0];
        Score     = [S4,S3,S2,S1,S0];
        CarryIn   = [C4,C3,C2,C1, 0];
        CarryOut  = [ X,C4,C3,C2,C1];
        ten       = [ 0, 1, 0, 1, 0];
        minus_ten = [ 1, 0, 1, 1, 0];

        S4,S3,S2,S1,S0 istype 'reg' ;

" Input Multiplexer
        Data     =  Add10 &  Sub10 & Card 
                 # !Add10 &  Sub10 & ten
                 #  Add10 & !Sub10 & minus_ten;

equations
        Score   := Data $ Score $ CarryIn;

        CarryOut = Data & Score # (Data # Score) & CarryIn;  

        Score.ar = !Clr;

        Score.c  = AddClk;

        is_Ace   = Card == 1;

trace
       ([AddClk,Clr,Add10,Sub10,Card] -> [Score,is_Ace,CarryOut])
test_vectors 
       ([AddClk,Clr,Add10,Sub10,Card] -> [Score,is_Ace])
        [   L  , L ,  H  ,  H  ,  X ] -> [  0  ,   L  ]; "Clear
        [   C  , H ,  H  ,  H  ,  7 ] -> [  7  ,   L  ];
        [   C  , L ,  H  ,  H  , 10 ] -> [ 17  ,   L  ];
        [   L  , L ,  H  ,  H  ,  X ] -> [  0  ,   L  ]; "Clear
        [   C  , H ,  H  ,  H  ,  1 ] -> [  1  ,   H  ];
        [   C  , H ,  L  ,  H  ,  1 ] -> [ 11  ,   H  ]; "Add 10        
        [   C  , H ,  H  ,  H  ,  4 ] -> [ 15  ,   L  ];
        [   C  , H ,  H  ,  H  ,  8 ] -> [ 23  ,   L  ];        
        [   C  , H ,  H  ,  L  ,  8 ] -> [ 13  ,   L  ]; "Subtract 10 
        [   C  , H ,  H  ,  H  ,  5 ] -> [ 18  ,   L  ];

end MuxAdd