?? fpls.abl
字號:
module FPLS
title 'Feature test for F157
Bob Lockhart Data I/O Redmond WA 4 Aug 1990'
fpls device 'F157';
C,L,H,X,Z = .C.,0,1,.X.,.Z.;
Clk,Ena pin 1,11;
I0,I1,I2,I3 pin 2,3,4,5;
B0,B1,B2,B3,B4,B5 pin 6,7,8,9,12,19;
F0,F1,F2,F3 pin 13,14,15,16;
F4,F5 pin 17,18;
mode = [B2,B1,B0];
M_norm = [ 0, 0, 0];
M_Preset = [ 1, 0, 0];
M_Reset = [ 0, 1, 0];
M_Load = [ 0, 0, 1];
"Configure Flip/Flops F0 and F1 with ISTYPE statement
F0 istype 'reg_JK ,invert';
F1 istype 'reg_JKD,invert';
F4 istype 'reg_JK ,invert';
F5 istype 'reg_JK ,invert';
equations
"Output enable for bank A registers
[F1,F0].OE = !Ena; " Enable controlled by pin 11
"Clock Equations
[F1,F0].C = Clk;
"Flip/Flop control term
F1.FC = I0;
"Flip/Flop equations
F0.J = I1;
F0.K = I2;
F1.J = I1;
F1.K = I3;
"Feedback equations
B5 = F1.Q & F0.Q;
"Preset,Reset, and Load
[F1,F0].PR = B2;
[F1,F0].RE = B1;
[F1,F0].L = B0;
@page
test_vectors 'F1 in D type'
([Clk,Ena,I0,I1,I2,I3,mode ] -> [!F0,!F1, B5])
[ 0 , L , 0, 0, 0, 0,M_Reset ] -> [ 0 , 0 , 0 ]; "Reset
[ C , L , 0, 0, 0, 0,M_norm ] -> [ 0 , 0 , 0 ];
[ C , L , 0, 1, 0, 0,M_norm ] -> [ 1 , 1 , 1 ]; "High
[ C , L , 0, 1, 1, 0,M_norm ] -> [ 0 , 1 , 0 ]; "Toggle F0
[ C , L , 0, 1, 1, 0,M_norm ] -> [ 1 , 1 , 1 ]; "Toggle F0
[ C , L , 0, 0, 0, 0,M_norm ] -> [ 1 , 0 , 0 ]; "Hold F0
[ C , L , 0, 0, 1, 0,M_norm ] -> [ 0 , 0 , 0 ]; "Low
[ 0 , L , 0, 0, 1, 0,M_Preset ] -> [ 1 , 1 , 1 ]; "Preset
[ C , L , 0, 1, 1, 0,M_norm ] -> [ 0 , 1 , 0 ]; "Toggle F0
test_vectors 'F1 in JK type'
([Clk,Ena,I0,I1,I2,I3,mode ] -> [!F0,!F1, B5])
[ 0 , L , 1, 0, 0, 0,M_Reset ] -> [ 0 , 0 , 0 ]; "Reset
[ C , L , 1, 1, 1, 1,M_norm ] -> [ 1 , 1 , 1 ]; "Toggle
[ C , L , 1, 1, 1, 1,M_norm ] -> [ 0 , 0 , 0 ]; "Toggle
[ C , L , 1, 1, 0, 0,M_norm ] -> [ 1 , 1 , 1 ]; "High
[ C , L , 1, 0, 0, 0,M_norm ] -> [ 1 , 1 , 1 ]; "Hold
[ C , L , 1, 0, 1, 1,M_norm ] -> [ 0 , 0 , 0 ]; "Low
[ C , H , 1, 1, 1, 1,M_norm ] -> [ Z , Z , 1 ]; "Toggle
[ C , H , 1, 1, 1, 1,M_norm ] -> [ Z , Z , 0 ]; "Toggle
test_vectors 'load'
([Clk,Ena,I0,I1,I2,I3,mode ,!F0,!F1] -> [!F0,!F1, B5])
[ 0 , L , 1, 0, 0, 0,M_Reset, X , X ] -> [ 0 , 0 , 0 ]; "Reset
[ C , H , 1, 0, 0, 0,M_Load , 1 , 0 ] -> [ X , X , 0 ]; "Load
[ 0 , L , 1, 0, 0, 0,M_norm , X , X ] -> [ 1 , 0 , 0 ]; "Test
[ C , L , 1, 1, 1, 1,M_norm , X , X ] -> [ 0 , 1 , 0 ]; "Toggle
equations
"Output enable for bank B registers
" [F5,F4].OE = [1,1];
" Always enabled
" Clock Equations
[F5,F4].C = Clk;
"Async Preset Equation
[F5,F4].PR = !B3;
"Equations for toggel counter
[F4.J,F4.K] = [1,1];
[F5.J,F5.K] = !F4.Q;
test_vectors 'toggle counter'
([Clk,Ena,B3] -> [F5,F4])
[ 0 , 0 , 0] -> 0; " Reset
[ C , 0 , 1] -> 1;
[ C , 0 , 1] -> 2;
[ C , 0 , 1] -> 3;
[ C , 0 , 0] -> 0;
[ C , 1 , 1] -> 1; " Output always enabled
[ C , 0 , 1] -> 2;
[ 0 , 0 , 0] -> 0; " Async Reset
end
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -