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<DD style="FLOAT: left">更新于2008-05-28 04:40:25 </DD></DL></DIV>
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<P><STRONG>2.6.1 Verilog基本模塊</STRONG> <BR><BR>1．觸發器的Verilog實現
<BR><BR>時序電路是高速電路的主要應用類型，其特點是任意時刻電路產生的穩定輸出不僅與當前的輸入有關，而且還與電路過去時刻的輸入有關。時序電路的基本單元就是觸發器。下面介紹幾種常見同步觸發器的Verilog實現。
</P>
<UL>
<LI>同步RS觸發器 </LI></UL>
<P>RS觸發器分為同步觸發器和異步觸發器，二者的區別在于同步觸發器有一個時鐘端clk，只有在時鐘端的信號上升（正觸發）或下降（負觸發）時，觸發器的輸出才會發生變化。下面以正觸發為例，給出其Verilog代碼實現。
<BR><BR>例2-15 正觸發型同步RS觸發器的Verilog實現。<BR><BR>module sy_rs_ff (clk, r, s, q, qb);
<BR> input clk, r, s;
<BR> output q, qb;
<BR> reg q;
<BR><BR> assign qb = ~ q;
<BR> always @(posedge clk) begin
<BR>
case({r, s})
<BR>
2'b00: q <= 0;
<BR>
2'b01: q <=
1; <BR> 2'b10:
q <= 0;
<BR>
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