module clk_1HZ(clk_24HZ,clk1);
input clk_24HZ;
output clk1;
parameter N=24000000;
reg[24:0]cont;
reg clk1;
always @(posedge clk_24HZ)
      begin
           if(cont==N)
              begin
                   cont<=0;
                   clk1<=0;
              end
            else
                begin
                cont<=cont+1;
                clk1<=1;
                end
       end
 endmodule