_EQ022 = !cont20 &  cont21 & !_LC3_C22
         #  cont21 & !_LC2_C19 & !_LC3_C22
         #  cont20 & !cont21 &  _LC2_C19 & !_LC3_C22;

-- Node name is ':88' = 'cont22' 
-- Equation name is 'cont22', location is LC3_C14, type is buried.
cont22   = DFFE( _EQ023, GLOBAL( clk_24HZ),  VCC,  VCC,  VCC);
  _EQ023 = !cont21 &  cont22 & !_LC3_C22
         #  cont22 & !_LC2_C14 & !_LC3_C22
         #  cont21 & !cont22 &  _LC2_C14 & !_LC3_C22;

-- Node name is ':87' = 'cont23' 
-- Equation name is 'cont23', location is LC7_C14, type is buried.
cont23   = DFFE( _EQ024, GLOBAL( clk_24HZ),  VCC,  VCC,  VCC);
  _EQ024 =  cont23 & !_LC3_C22 & !_LC5_C14
         # !cont23 & !_LC3_C22 &  _LC5_C14;

-- Node name is ':86' = 'cont24' 
-- Equation name is 'cont24', location is LC6_C14, type is buried.
cont24   = DFFE( _EQ025, GLOBAL( clk_24HZ),  VCC,  VCC,  VCC);
  _EQ025 = !cont23 &  cont24 & !_LC3_C22
         #  cont24 & !_LC3_C22 & !_LC5_C14
         #  cont23 & !cont24 & !_LC3_C22 &  _LC5_C14;

-- Node name is '|lpm_add_sub:115|addcore:adder|:143' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C22', type is buried 
_LC4_C22 = LCELL( _EQ026);
  _EQ026 =  cont0 &  cont1 &  cont2;

-- Node name is '|lpm_add_sub:115|addcore:adder|:147' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C22', type is buried 
_LC2_C22 = LCELL( _EQ027);
  _EQ027 =  cont0 &  cont1 &  cont2 &  cont3;

-- Node name is '|lpm_add_sub:115|addcore:adder|:155' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C16', type is buried 
_LC6_C16 = LCELL( _EQ028);
  _EQ028 =  cont4 &  cont5 &  _LC2_C22;

-- Node name is '|lpm_add_sub:115|addcore:adder|:159' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C13', type is buried 
_LC6_C13 = LCELL( _EQ029);
  _EQ029 =  cont6 &  _LC6_C16;

-- Node name is '|lpm_add_sub:115|addcore:adder|:167' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C16', type is buried 
_LC2_C16 = LCELL( _EQ030);
  _EQ030 =  cont6 &  cont7 &  cont8 &  _LC6_C16;

-- Node name is '|lpm_add_sub:115|addcore:adder|:171' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C13', type is buried 
_LC5_C13 = LCELL( _EQ031);
  _EQ031 =  cont9 &  _LC2_C16;

-- Node name is '|lpm_add_sub:115|addcore:adder|:179' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C13', type is buried 
_LC2_C13 = LCELL( _EQ032);
  _EQ032 =  cont9 &  cont10 &  cont11 &  _LC2_C16;

-- Node name is '|lpm_add_sub:115|addcore:adder|:183' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C17', type is buried 
_LC6_C17 = LCELL( _EQ033);
  _EQ033 =  cont12 &  _LC2_C13;

-- Node name is '|lpm_add_sub:115|addcore:adder|:191' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C17', type is buried 
_LC3_C17 = LCELL( _EQ034);
  _EQ034 =  cont12 &  cont13 &  cont14 &  _LC2_C13;

-- Node name is '|lpm_add_sub:115|addcore:adder|:195' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C17', type is buried 
_LC2_C17 = LCELL( _EQ035);
  _EQ035 =  cont15 &  _LC3_C17;

-- Node name is '|lpm_add_sub:115|addcore:adder|:203' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C19', type is buried 
_LC5_C19 = LCELL( _EQ036);
  _EQ036 =  cont16 &  cont17 &  _LC2_C17;

-- Node name is '|lpm_add_sub:115|addcore:adder|:211' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C19', type is buried 
_LC2_C19 = LCELL( _EQ037);
  _EQ037 =  cont18 &  cont19 &  _LC5_C19;

-- Node name is '|lpm_add_sub:115|addcore:adder|:215' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C14', type is buried 
_LC2_C14 = LCELL( _EQ038);
  _EQ038 =  cont20 &  _LC2_C19;

-- Node name is '|lpm_add_sub:115|addcore:adder|:223' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C14', type is buried 
_LC5_C14 = LCELL( _EQ039);
  _EQ039 =  cont20 &  cont21 &  cont22 &  _LC2_C19;

-- Node name is '~3~1' 
-- Equation name is '~3~1', location is LC8_C13, type is buried.
-- synthesized logic cell 
_LC8_C13 = LCELL( _EQ040);
  _EQ040 = !cont9
         # !cont10
         #  cont11
         # !cont12;

-- Node name is '~3~2' 
-- Equation name is '~3~2', location is LC1_C16, type is buried.
-- synthesized logic cell 
_LC1_C16 = LCELL( _EQ041);
  _EQ041 =  cont5
         #  cont6
         #  cont7
         #  cont8;

-- Node name is '~3~3' 
-- Equation name is '~3~3', location is LC8_C16, type is buried.
-- synthesized logic cell 
_LC8_C16 = LCELL( _EQ042);
  _EQ042 =  _LC8_C13
         #  _LC1_C16
         #  cont3
         #  cont4;

-- Node name is '~3~4' 
-- Equation name is '~3~4', location is LC8_C14, type is buried.
-- synthesized logic cell 
_LC8_C14 = LCELL( _EQ043);
  _EQ043 = !cont21
         # !cont22
         # !cont24
         #  cont23;

-- Node name is '~3~5' 
-- Equation name is '~3~5', location is LC4_C19, type is buried.
-- synthesized logic cell 
_LC4_C19 = LCELL( _EQ044);
  _EQ044 = !cont17
         # !cont18
         # !cont19
         #  cont20;

-- Node name is '~3~6' 
-- Equation name is '~3~6', location is LC5_C17, type is buried.
-- synthesized logic cell 
_LC5_C17 = LCELL( _EQ045);
  _EQ045 = !cont13
         #  cont14
         #  cont15
         #  cont16;

-- Node name is '~3~7' 
-- Equation name is '~3~7', location is LC1_C19, type is buried.
-- synthesized logic cell 
_LC1_C19 = LCELL( _EQ046);
  _EQ046 =  _LC8_C16
         #  _LC8_C14
         #  _LC4_C19
         #  _LC5_C17;

-- Node name is ':3' 
-- Equation name is '_LC3_C22', type is buried 
!_LC3_C22 = _LC3_C22~NOT;
_LC3_C22~NOT = LCELL( _EQ047);
  _EQ047 =  cont0
         #  cont1
         #  cont2
         #  _LC1_C19;

-- Node name is ':114' 
-- Equation name is '_LC1_C22', type is buried 
_LC1_C22 = DFFE( _EQ048, GLOBAL( clk_24HZ),  VCC,  VCC,  VCC);
  _EQ048 =  cont2
         #  _LC1_C19
         #  cont1
         #  cont0;



Project Information                                    e:\datacont\clk_1hz.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 32,020K