package slotwidth is
constant sreg_width :integer:=20;
end slotwidth;
use work.defcon.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY aclink2 IS
		PORT(
		bit_clk	,key1	: IN	STD_LOGIC;
		slot :buffer std_logic_vector(3 downto 0);
		sl:buffer std_logic;
		
		slotdata:out std_logic_vector(19 downto 0);
		sdata_out:out std_logic;
		sync	: OUT	STD_LOGIC);
END aclink2;

architecture behav of aclink2 is
signal slotdata_sig1:std_logic_vector(19 downto 0):="00000000000000000000";
signal se,play_sig1:std_logic;
component sreg1 is
port(sl,se,clk:in std_logic;
	datain:in std_logic_vector(sreg_width-1 downto 0);
	q:out std_logic);
end component;
begin
slotdata<=slotdata_sig1;
se<='0';
u1:sreg1 port map(sl,se,bit_clk,slotdata_sig1,sdata_out);
process(bit_clk)
variable counter: std_logic_vector(7 downto 0);
begin
if(bit_clk'event and bit_clk='1')then
if(play_sig1='1')then
if(conv_integer(counter)<16)then
sync<='1';
counter:=counter+1;
else
sync<='0';
counter:=counter+1;
end if;
if(counter<1)then
slot<="1100";
elsif(counter<17)then
slot<="0000";
elsif(counter<37)then
slot<="0001";
elsif(counter<57)then
slot<="0010";
elsif(counter<77)then
slot<="0011";
elsif(counter<97)then
slot<="0100";
elsif(counter<117)then
slot<="0101";
elsif(counter<137)then
slot<="0110";
elsif(counter<157)then
slot<="0111";
elsif(counter<177)then
slot<="1000";
elsif(counter<197)then
slot<="1001";
elsif(counter<217)then
slot<="1010";
elsif(counter<237)then
slot<="1011";
else
slot<="1100";
end if;
if(counter=1)then
sl<='0';
elsif(counter=17)then
sl<='0';
elsif(counter=37)then
sl<='0';
elsif(counter=57)then
sl<='0';
elsif(counter=77)then
sl<='0';
elsif(counter=97)then
sl<='0';
elsif(counter=117)then
sl<='0';
elsif(counter=137)then
sl<='0';
elsif(counter=157)then
sl<='0';
elsif(counter=177)then
sl<='0';
elsif(counter=197)then
sl<='0';
elsif(counter=217)then
sl<='0';
elsif(counter=237)then
sl<='0';
else
sl<='1';
end if;
else 
sync<='0';
sl<='0';
slot<="0000";
end if;
end if;
end process;
process
begin
if(play_sig1='1')then
case slot is
when "0000"=>slotdata_sig1<="10011000000000000000";
when "0001"=>slotdata_sig1<="00000000000000000000";
when "0010"=>slotdata_sig1<="00000000001111111111";
when "0011"=>slotdata_sig1<="11111111110000000000";
when "0100"=>slotdata_sig1<="00000000000000000000";
when "0101"=>slotdata_sig1<="00000000000000000000";
when "0110"=>slotdata_sig1<="00000000000000000000";
when "0111"=>slotdata_sig1<="00000000000000000000";
when "1000"=>slotdata_sig1<="00000000000000000000";
when "1001"=>slotdata_sig1<="00000000000000000000";
when "1010"=>slotdata_sig1<="00000000000000000000";
when "1011"=>slotdata_sig1<="00000000000000000000";
when others=>slotdata_sig1<="00000000000000000000";
end case;
else
slotdata_sig1<="00000000000000000000";
end if;
end process;
process(key1)
begin
if(key1'event and key1='0')then
	play_sig1<=not play_sig1;
end if;
end process;
end behav;