package defcon is
constant sreg_width :integer:=20;
end defcon;
use work.defcon.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sreg3 is
port(sl,clk,q:in std_logic;
	dataout:out std_logic_vector(sreg_width-1 downto 0));
end sreg3;
architecture behav of sreg3 is
signal tmpreg:std_logic_vector(sreg_width-1 downto 0);
begin
process(clk)
begin
		if(clk'event and clk='0')then
				for i in sreg_width-1 downto 1 loop
					tmpreg(i)<=tmpreg(i-1);
				end loop;
				tmpreg(0)<=q;	
				if(sl='0')then
					dataout<=tmpreg;
				end if;
		end if;
end process;
end behav;