LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Speaker IS
    PORT (  clk1   : IN STD_LOGIC;
             Tone1 : IN INTEGER RANGE 0 TO 16#7FF#;
             SpkS  : OUT STD_LOGIC  );
END;
ARCHITECTURE one OF Speaker IS
    SIGNAL   PreCLK , FullSpkS : STD_LOGIC;
    BEGIN
 DivideCLK : PROCESS(clk1)
        VARIABLE Count4 : INTEGER RANGE 0 TO 15;
    BEGIN
       PreCLK <= '0';    --將CLK進(jìn) 11分頻，PreCLK為C L 11K 6分頻
       IF Count4 > 11  THEN  PreCLK <= '1';  Count4 := 0;
       ELSIF clk1'EVENT AND clk1='1' THEN  Count4 := Count4 + 1;            
       END IF;
    END PROCESS;
GenSpkS : PROCESS(PreCLK, Tone1)
        VARIABLE Count11 : INTEGER RANGE 0 TO 16#7FF#;
               BEGIN            -- 11位可預(yù)置計數(shù)器
      IF PreCLK'EVENT AND PreCLK = '1' THEN
        IF  Count11=16#7FF# THEN  
           Count11 := Tone1; FullSpkS <= '1';                
           ELSE Count11:=Count11 + 1; FullSpkS <= '0';                
        END IF;
      END IF;
    END PROCESS;
    DelaySpkS : PROCESS(FullSpkS) 
        VARIABLE Count2 : STD_LOGIC;
            BEGIN 
        IF FullSpkS'EVENT AND FullSpkS = '1' THEN Count2 := NOT Count2;
            IF Count2 = '1' THEN  SpkS <= '1';
                            ELSE     SpkS <= '0';
            END IF;
        END IF;
    END PROCESS;
END;