?? lock.map.rpt
字號:
Analysis & Synthesis report for lock
Wed Jan 09 14:57:29 2008
Version 5.0 Build 148 04/26/2005 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. General Register Statistics
8. Inverted Register Statistics
9. Analysis & Synthesis Equations
10. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Jan 09 14:57:29 2008 ;
; Quartus II Version ; 5.0 Build 148 04/26/2005 SJ Web Edition ;
; Revision Name ; lock ;
; Top-level Entity Name ; lock ;
; Family ; Cyclone II ;
; Total combinational functions ; 10 ;
; Total registers ; 11 ;
; Total pins ; 15 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+-----------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------+--------------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Device ; EP2C35F672C6 ; ;
; Top-level entity name ; lock ; lock ;
; Family name ; Cyclone II ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; Maximum DSP Block Usage ; -1 ; -1 ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Cyclone II ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Maximum Number of M4K Memory Blocks ; -1 ; -1 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+--------------------------------------------------------------------+--------------+---------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------+
; lock.vhd ; yes ; User VHDL File ; C:/Documents and Settings/student/桌面/lock/lock.vhd ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total combinational functions ; 10 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 8 ;
; -- 3 input functions ; 0 ;
; -- <=2 input functions ; 2 ;
; -- Combinational cells for routing ; 0 ;
; Logic elements by mode ; ;
; -- normal mode ; 10 ;
; -- arithmetic mode ; 0 ;
; Total registers ; 11 ;
; I/O pins ; 15 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 11 ;
; Total fan-out ; 77 ;
; Average fan-out ; 2.14 ;
+---------------------------------------------+-------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; |lock ; 10 (10) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 15 ; 0 ; |lock ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 11 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 11 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 8 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; ledg~reg0 ; 1 ;
; key[0] ; 1 ;
; Total number of inverted registers = 2 ; ;
+----------------------------------------+---------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Documents and Settings/student/桌面/lock/lock.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Web Edition
Info: Processing started: Wed Jan 09 14:57:27 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lock -c lock
Info: Found 2 design units, including 1 entities, in source file lock.vhd
Info: Found design unit 1: lock-lock
Info: Found entity 1: lock
Info: Elaborating entity "lock" for the top level hierarchy
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 36 device resources after synthesis - the final resource count might be different
Info: Implemented 13 input pins
Info: Implemented 2 output pins
Info: Implemented 21 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Processing ended: Wed Jan 09 14:57:29 2008
Info: Elapsed time: 00:00:03
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