?? lock.tan.qmsg

?? 以QuatusⅡ為平臺
?? QMSG
?? 第 1 頁 / 共 3 頁
字號:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register key\[0\] register key\[5\] 272.63 MHz 3.668 ns Internal " "Info: Clock \"clk\" has Internal fmax of 272.63 MHz between source register \"key\[0\]\" and destination register \"key\[5\]\" (period= 3.668 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.449 ns + Longest register register " "Info: + Longest register to register delay is 3.449 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key\[0\] 1 REG LCFF_X64_Y18_N15 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X64_Y18_N15; Fanout = 1; REG Node = 'key\[0\]'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "" { key[0] } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.472 ns) + CELL(0.447 ns) 0.919 ns equal~92 2 COMB LCCOMB_X64_Y18_N28 1 " "Info: 2: + IC(0.472 ns) + CELL(0.447 ns) = 0.919 ns; Loc. = LCCOMB_X64_Y18_N28; Fanout = 1; COMB Node = 'equal~92'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "0.919 ns" { key[0] equal~92 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.474 ns) + CELL(0.447 ns) 1.840 ns equal~96 3 COMB LCCOMB_X64_Y18_N2 3 " "Info: 3: + IC(0.474 ns) + CELL(0.447 ns) = 1.840 ns; Loc. = LCCOMB_X64_Y18_N2; Fanout = 3; COMB Node = 'equal~96'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "0.921 ns" { equal~92 equal~96 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.271 ns) + CELL(0.428 ns) 2.539 ns key\[0\]~7 4 COMB LCCOMB_X64_Y18_N24 8 " "Info: 4: + IC(0.271 ns) + CELL(0.428 ns) = 2.539 ns; Loc. = LCCOMB_X64_Y18_N24; Fanout = 8; COMB Node = 'key\[0\]~7'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "0.699 ns" { equal~96 key[0]~7 } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.237 ns) + CELL(0.673 ns) 3.449 ns key\[5\] 5 REG LCFF_X64_Y18_N1 1 " "Info: 5: + IC(0.237 ns) + CELL(0.673 ns) = 3.449 ns; Loc. = LCFF_X64_Y18_N1; Fanout = 1; REG Node = 'key\[5\]'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "0.910 ns" { key[0]~7 key[5] } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.995 ns 57.84 % " "Info: Total cell delay = 1.995 ns ( 57.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.454 ns 42.16 % " "Info: Total interconnect delay = 1.454 ns ( 42.16 % )" {  } {  } 0}  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "3.449 ns" { key[0] equal~92 equal~96 key[0]~7 key[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.449 ns" { key[0] equal~92 equal~96 key[0]~7 key[5] } { 0.000ns 0.472ns 0.474ns 0.271ns 0.237ns } { 0.000ns 0.447ns 0.447ns 0.428ns 0.673ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.681 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "" { clk } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.063 ns clk~clkctrl 2 COMB CLKCTRL_G2 11 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.070 ns) + CELL(0.548 ns) 2.681 ns key\[5\] 3 REG LCFF_X64_Y18_N1 1 " "Info: 3: + IC(1.070 ns) + CELL(0.548 ns) = 2.681 ns; Loc. = LCFF_X64_Y18_N1; Fanout = 1; REG Node = 'key\[5\]'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "1.618 ns" { clk~clkctrl key[5] } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.493 ns 55.69 % " "Info: Total cell delay = 1.493 ns ( 55.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.188 ns 44.31 % " "Info: Total interconnect delay = 1.188 ns ( 44.31 % )" {  } {  } 0}  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "2.681 ns" { clk clk~clkctrl key[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.681 ns" { clk clk~combout clk~clkctrl key[5] } { 0.000ns 0.000ns 0.118ns 1.070ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.681 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "" { clk } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.063 ns clk~clkctrl 2 COMB CLKCTRL_G2 11 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.070 ns) + CELL(0.548 ns) 2.681 ns key\[0\] 3 REG LCFF_X64_Y18_N15 1 " "Info: 3: + IC(1.070 ns) + CELL(0.548 ns) = 2.681 ns; Loc. = LCFF_X64_Y18_N15; Fanout = 1; REG Node = 'key\[0\]'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "1.618 ns" { clk~clkctrl key[0] } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.493 ns 55.69 % " "Info: Total cell delay = 1.493 ns ( 55.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.188 ns 44.31 % " "Info: Total interconnect delay = 1.188 ns ( 44.31 % )" {  } {  } 0}  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "2.681 ns" { clk clk~clkctrl key[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.681 ns" { clk clk~combout clk~clkctrl key[0] } { 0.000ns 0.000ns 0.118ns 1.070ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } }  } 0}  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "2.681 ns" { clk clk~clkctrl key[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.681 ns" { clk clk~combout clk~clkctrl key[5] } { 0.000ns 0.000ns 0.118ns 1.070ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } } { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "2.681 ns" { clk clk~clkctrl key[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.681 ns" { clk clk~combout clk~clkctrl key[0] } { 0.000ns 0.000ns 0.118ns 1.070ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.255 ns + " "Info: + Micro clock to output delay of source is 0.255 ns" {  } { { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 24 -1 0 } }  } 0}  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "3.449 ns" { key[0] equal~92 equal~96 key[0]~7 key[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.449 ns" { key[0] equal~92 equal~96 key[0]~7 key[5] } { 0.000ns 0.472ns 0.474ns 0.271ns 0.237ns } { 0.000ns 0.447ns 0.447ns 0.428ns 0.673ns } } } { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "2.681 ns" { clk clk~clkctrl key[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.681 ns" { clk clk~combout clk~clkctrl key[5] } { 0.000ns 0.000ns 0.118ns 1.070ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } } { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "2.681 ns" { clk clk~clkctrl key[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.681 ns" { clk clk~combout clk~clkctrl key[0] } { 0.000ns 0.000ns 0.118ns 1.070ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "ledg~reg0 lockon clk 4.758 ns register " "Info: tsu for register \"ledg~reg0\" (data pin = \"lockon\", clock pin = \"clk\") is 4.758 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.475 ns + Longest pin register " "Info: + Longest pin to register delay is 7.475 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.805 ns) 0.805 ns lockon 1 PIN PIN_G26 3 " "Info: 1: + IC(0.000 ns) + CELL(0.805 ns) = 0.805 ns; Loc. = PIN_G26; Fanout = 3; PIN Node = 'lockon'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "" { lockon } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.414 ns) + CELL(0.447 ns) 6.666 ns ledg~14 2 COMB LCCOMB_X64_Y18_N10 2 " "Info: 2: + IC(5.414 ns) + CELL(0.447 ns) = 6.666 ns; Loc. = LCCOMB_X64_Y18_N10; Fanout = 2; COMB Node = 'ledg~14'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "5.861 ns" { lockon ledg~14 } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.280 ns) 7.389 ns ledg~15 3 COMB LCCOMB_X64_Y18_N16 1 " "Info: 3: + IC(0.443 ns) + CELL(0.280 ns) = 7.389 ns; Loc. = LCCOMB_X64_Y18_N16; Fanout = 1; COMB Node = 'ledg~15'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "0.723 ns" { ledg~14 ledg~15 } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 7.475 ns ledg~reg0 4 REG LCFF_X64_Y18_N17 1 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 7.475 ns; Loc. = LCFF_X64_Y18_N17; Fanout = 1; REG Node = 'ledg~reg0'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "0.086 ns" { ledg~15 ledg~reg0 } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.618 ns 21.65 % " "Info: Total cell delay = 1.618 ns ( 21.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.857 ns 78.35 % " "Info: Total interconnect delay = 5.857 ns ( 78.35 % )" {  } {  } 0}  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "7.475 ns" { lockon ledg~14 ledg~15 ledg~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.475 ns" { lockon lockon~combout ledg~14 ledg~15 ledg~reg0 } { 0.000ns 0.000ns 5.414ns 0.443ns 0.000ns } { 0.000ns 0.805ns 0.447ns 0.280ns 0.086ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.681 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "" { clk } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.063 ns clk~clkctrl 2 COMB CLKCTRL_G2 11 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.070 ns) + CELL(0.548 ns) 2.681 ns ledg~reg0 3 REG LCFF_X64_Y18_N17 1 " "Info: 3: + IC(1.070 ns) + CELL(0.548 ns) = 2.681 ns; Loc. = LCFF_X64_Y18_N17; Fanout = 1; REG Node = 'ledg~reg0'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "1.618 ns" { clk~clkctrl ledg~reg0 } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.493 ns 55.69 % " "Info: Total cell delay = 1.493 ns ( 55.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.188 ns 44.31 % " "Info: Total interconnect delay = 1.188 ns ( 44.31 % )" {  } {  } 0}  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "2.681 ns" { clk clk~clkctrl ledg~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.681 ns" { clk clk~combout clk~clkctrl ledg~reg0 } { 0.000ns 0.000ns 0.118ns 1.070ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } }  } 0}  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "7.475 ns" { lockon ledg~14 ledg~15 ledg~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.475 ns" { lockon lockon~combout ledg~14 ledg~15 ledg~reg0 } { 0.000ns 0.000ns 5.414ns 0.443ns 0.000ns } { 0.000ns 0.805ns 0.447ns 0.280ns 0.086ns } } } { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "2.681 ns" { clk clk~clkctrl ledg~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.681 ns" { clk clk~combout clk~clkctrl ledg~reg0 } { 0.000ns 0.000ns 0.118ns 1.070ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk ledg ledg~reg0 7.175 ns register " "Info: tco from clock \"clk\" to destination pin \"ledg\" through register \"ledg~reg0\" is 7.175 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.681 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "" { clk } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.063 ns clk~clkctrl 2 COMB CLKCTRL_G2 11 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.070 ns) + CELL(0.548 ns) 2.681 ns ledg~reg0 3 REG LCFF_X64_Y18_N17 1 " "Info: 3: + IC(1.070 ns) + CELL(0.548 ns) = 2.681 ns; Loc. = LCFF_X64_Y18_N17; Fanout = 1; REG Node = 'ledg~reg0'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "1.618 ns" { clk~clkctrl ledg~reg0 } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.493 ns 55.69 % " "Info: Total cell delay = 1.493 ns ( 55.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.188 ns 44.31 % " "Info: Total interconnect delay = 1.188 ns ( 44.31 % )" {  } {  } 0}  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "2.681 ns" { clk clk~clkctrl ledg~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.681 ns" { clk clk~combout clk~clkctrl ledg~reg0 } { 0.000ns 0.000ns 0.118ns 1.070ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.255 ns + " "Info: + Micro clock to output delay of source is 0.255 ns" {  } { { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.239 ns + Longest register pin " "Info: + Longest register to pin delay is 4.239 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ledg~reg0 1 REG LCFF_X64_Y18_N17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X64_Y18_N17; Fanout = 1; REG Node = 'ledg~reg0'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "" { ledg~reg0 } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.701 ns) + CELL(2.538 ns) 4.239 ns ledg 2 PIN PIN_AE22 0 " "Info: 2: + IC(1.701 ns) + CELL(2.538 ns) = 4.239 ns; Loc. = PIN_AE22; Fanout = 0; PIN Node = 'ledg'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "4.239 ns" { ledg~reg0 ledg } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.538 ns 59.87 % " "Info: Total cell delay = 2.538 ns ( 59.87 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.701 ns 40.13 % " "Info: Total interconnect delay = 1.701 ns ( 40.13 % )" {  } {  } 0}  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "4.239 ns" { ledg~reg0 ledg } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.239 ns" { ledg~reg0 ledg } { 0.000ns 1.701ns } { 0.000ns 2.538ns } } }  } 0}  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "2.681 ns" { clk clk~clkctrl ledg~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.681 ns" { clk clk~combout clk~clkctrl ledg~reg0 } { 0.000ns 0.000ns 0.118ns 1.070ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } } { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "4.239 ns" { ledg~reg0 ledg } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.239 ns" { ledg~reg0 ledg } { 0.000ns 1.701ns } { 0.000ns 2.538ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "key\[0\] keyin\[0\] clk 0.998 ns register " "Info: th for register \"key\[0\]\" (data pin = \"keyin\[0\]\", clock pin = \"clk\") is 0.998 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.681 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "" { clk } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.063 ns clk~clkctrl 2 COMB CLKCTRL_G2 11 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.070 ns) + CELL(0.548 ns) 2.681 ns key\[0\] 3 REG LCFF_X64_Y18_N15 1 " "Info: 3: + IC(1.070 ns) + CELL(0.548 ns) = 2.681 ns; Loc. = LCFF_X64_Y18_N15; Fanout = 1; REG Node = 'key\[0\]'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "1.618 ns" { clk~clkctrl key[0] } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.493 ns 55.69 % " "Info: Total cell delay = 1.493 ns ( 55.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.188 ns 44.31 % " "Info: Total interconnect delay = 1.188 ns ( 44.31 % )" {  } {  } 0}  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "2.681 ns" { clk clk~clkctrl key[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.681 ns" { clk clk~combout clk~clkctrl key[0] } { 0.000ns 0.000ns 0.118ns 1.070ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.170 ns + " "Info: + Micro hold delay of destination is 0.170 ns" {  } { { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.853 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns keyin\[0\] 1 PIN PIN_N25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N25; Fanout = 2; PIN Node = 'keyin\[0\]'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "" { keyin[0] } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.153 ns) 1.767 ns key\[0\]~40 2 COMB LCCOMB_X64_Y18_N14 1 " "Info: 2: + IC(0.669 ns) + CELL(0.153 ns) = 1.767 ns; Loc. = LCCOMB_X64_Y18_N14; Fanout = 1; COMB Node = 'key\[0\]~40'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "0.822 ns" { keyin[0] key[0]~40 } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.853 ns key\[0\] 3 REG LCFF_X64_Y18_N15 1 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.853 ns; Loc. = LCFF_X64_Y18_N15; Fanout = 1; REG Node = 'key\[0\]'" {  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "0.086 ns" { key[0]~40 key[0] } "NODE_NAME" } "" } } { "lock.vhd" "" { Text "C:/Documents and Settings/student/桌面/lock/lock.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.184 ns 63.90 % " "Info: Total cell delay = 1.184 ns ( 63.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.669 ns 36.10 % " "Info: Total interconnect delay = 0.669 ns ( 36.10 % )" {  } {  } 0}  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "1.853 ns" { keyin[0] key[0]~40 key[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.853 ns" { keyin[0] keyin[0]~combout key[0]~40 key[0] } { 0.000ns 0.000ns 0.669ns 0.000ns } { 0.000ns 0.945ns 0.153ns 0.086ns } } }  } 0}  } { { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "2.681 ns" { clk clk~clkctrl key[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.681 ns" { clk clk~combout clk~clkctrl key[0] } { 0.000ns 0.000ns 0.118ns 1.070ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } } { "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" "" { Report "C:/Documents and Settings/student/桌面/lock/db/lock_cmp.qrpt" Compiler "lock" "UNKNOWN" "V1" "C:/Documents and Settings/student/桌面/lock/db/lock.quartus_db" { Floorplan "C:/Documents and Settings/student/桌面/lock/" "" "1.853 ns" { keyin[0] key[0]~40 key[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.853 ns" { keyin[0] keyin[0]~combout key[0]~40 key[0] } { 0.000ns 0.000ns 0.669ns 0.000ns } { 0.000ns 0.945ns 0.153ns 0.086ns } } }  } 0}
?? 文件大小 184 K
?? 上傳用戶 wy50094777
?? 所屬分類 VHDL/FPGA/Verilog
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