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8.3 阻塞賦值與無阻塞賦值</div>
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<div class="Element13"><div class="Element12" id="code00261"><pre class="Element12">blocking_assignment ::= <span style="color: #008000">// 引用自附錄A.6.2</span>
variable_lvalue <strong><span style="color: #FF0000">=</span></strong> delay_or_event_control expression
| hierarchical_dynamic_array_variable_identifier <strong><span style="color: #FF0000">=</span></strong> dynamic_array_new
| [implicit_class_handle<strong><span style="color: #FF0000">.</span></strong>|class_scope|package_scope]hierarchical_variable_identifier
select <strong><span style="color: #FF0000">=</span></strong> class_new
| operator_assignment
operator_assignment ::= variable_lvalue assignment_operator expression
assignment_operator ::=
<strong><span style="color: #FF0000">=</span></strong> | <strong><span style="color: #FF0000">+=</span></strong> | <strong><span style="color: #FF0000">-=</span></strong> | <strong><span style="color: #FF0000">*=</span></strong> | <strong><span style="color: #FF0000">/=</span></strong> | <strong><span style="color: #FF0000">%=</span></strong> | <strong><span style="color: #FF0000">&=</span></strong> | <strong><span style="color: #FF0000">|=</span></strong> | <strong><span style="color: #FF0000">^=</span></strong> | <strong><span style="color: #FF0000"><<=</span></strong> | <strong><span style="color: #FF0000">>>=</span></strong> | <strong><span style="color: #FF0000"><<<=</span></strong> | <strong><span style="color: #FF0000">>>>=</span></strong>
nonblocking_assignment ::= variable_lvalue <strong><span style="color: #FF0000"><=</span></strong> [delay_or_event_control] expression</pre></div></div>
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<strong>語法 8-2—阻塞與無阻塞賦值語法（摘錄自附錄A）</strong></p><p class="Element10">
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下列的賦值語句在Verilog-2001和SystemVerilog中都是合法的： </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00262"><pre class="Element12"><span style="color: #800080">#</span><span style="color: #FF0000">1</span> r <span style="color: #800080">=</span> a<span style="color: #800080">;</span>
r <span style="color: #800080">= #</span><span style="color: #FF0000">1</span> a<span style="color: #800080">;</span>
r <span style="color: #800080"><=</span> <span style="color: #800080">#</span><span style="color: #FF0000">1</span> a<span style="color: #800080">;</span>
r <span style="color: #800080"><=</span> a<span style="color: #800080">;</span>
<span style="color: #800080">@</span>c r <span style="color: #800080">=</span> a<span style="color: #800080">;</span>
r <span style="color: #800080">= @</span>c a<span style="color: #800080">;</span>
r <span style="color: #800080"><= @</span>c a<span style="color: #800080">;</span></pre></div></div>
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在賦值語句中，SystemVerilog還允許指定一個時間單位，例如： </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00263"><pre class="Element12"><span style="color: #800080">#</span><span style="color: #FF0000">1</span><span style="color: #0000FF">ns</span> r <span style="color: #800080">=</span> a<span style="color: #800080">;</span>
r <span style="color: #800080">=</span> <span style="color: #800080">#</span><span style="color: #FF0000">1</span><span style="color: #0000FF">ns</span> a<span style="color: #800080">;</span>
r <span style="color: #800080"><=</span> <span style="color: #800080">#</span><span style="color: #FF0000">1</span><span style="color: #0000FF">ns</span> a<span style="color: #800080">;</span></pre></div></div>
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為自動變量進行無阻塞賦值是非法的。 </p>
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賦值語句左側的尺寸形成了右側表達式的關聯文。如果左側尺寸小于右側表達式尺寸，信息可能會丟失，并且可以給出警告信息。</p></div>
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