{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 07 22:39:21 2006 " "Info: Processing started: Mon Aug 07 22:39:21 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off Now_Floor_Disp -c Now_Floor_Disp " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off Now_Floor_Disp -c Now_Floor_Disp" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "Reset Now_Floor_Disp_Data\[0\] 5.000 ns Longest " "Info: Longest tpd from source pin \"Reset\" to destination pin \"Now_Floor_Disp_Data\[0\]\" is 5.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Reset 1 PIN PIN_24 25 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 25; PIN Node = 'Reset'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Floor_Disp/db/Now_Floor_Disp_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Floor_Disp/db/Now_Floor_Disp_cmp.qrpt" Compiler "Now_Floor_Disp" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Floor_Disp/db/Now_Floor_Disp.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Floor_Disp/" "" "" { Reset } "NODE_NAME" } "" } } { "Now_Floor_Disp.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Floor_Disp/Now_Floor_Disp.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.600 ns) 4.800 ns reduce_or~1101 2 COMB LC1 1 " "Info: 2: + IC(1.000 ns) + CELL(3.600 ns) = 4.800 ns; Loc. = LC1; Fanout = 1; COMB Node = 'reduce_or~1101'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Floor_Disp/db/Now_Floor_Disp_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Floor_Disp/db/Now_Floor_Disp_cmp.qrpt" Compiler "Now_Floor_Disp" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Floor_Disp/db/Now_Floor_Disp.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Floor_Disp/" "" "4.600 ns" { Reset reduce_or~1101 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 5.000 ns Now_Floor_Disp_Data\[0\] 3 PIN PIN_4 0 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 5.000 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'Now_Floor_Disp_Data\[0\]'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Floor_Disp/db/Now_Floor_Disp_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Floor_Disp/db/Now_Floor_Disp_cmp.qrpt" Compiler "Now_Floor_Disp" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Floor_Disp/db/Now_Floor_Disp.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Floor_Disp/" "" "0.200 ns" { reduce_or~1101 Now_Floor_Disp_Data[0] } "NODE_NAME" } "" } } { "Now_Floor_Disp.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Floor_Disp/Now_Floor_Disp.v" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 80.00 % " "Info: Total cell delay = 4.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 20.00 % " "Info: Total interconnect delay = 1.000 ns ( 20.00 % )" {  } {  } 0}  } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Floor_Disp/db/Now_Floor_Disp_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Floor_Disp/db/Now_Floor_Disp_cmp.qrpt" Compiler "Now_Floor_Disp" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Floor_Disp/db/Now_Floor_Disp.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Floor_Disp/" "" "5.000 ns" { Reset reduce_or~1101 Now_Floor_Disp_Data[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.000 ns" { Reset Reset~out reduce_or~1101 Now_Floor_Disp_Data[0] } { 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 0.200ns 3.600ns 0.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 07 22:39:21 2006 " "Info: Processing ended: Mon Aug 07 22:39:21 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}